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target/arm: Convert Cyclic Redundancy Check
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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20190904193059.26202-15-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@rth7680 @pm215
rth7680 authored and pm215 committed Sep 5, 2019
1 parent d0b2664 commit 6c35d53
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Showing 3 changed files with 72 additions and 65 deletions.
9 changes: 9 additions & 0 deletions target/arm/a32.decode
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Expand Up @@ -182,6 +182,15 @@ SMULTT .... 0001 0110 .... 0000 .... 1110 .... @rd0mn
}
MSR_imm .... 0011 0110 .... 1111 .... .... .... @msr_i r=1

# Cyclic Redundancy Check

CRC32B .... 0001 0000 .... .... 0000 0100 .... @rndm
CRC32H .... 0001 0010 .... .... 0000 0100 .... @rndm
CRC32W .... 0001 0100 .... .... 0000 0100 .... @rndm
CRC32CB .... 0001 0000 .... .... 0010 0100 .... @rndm
CRC32CH .... 0001 0010 .... .... 0010 0100 .... @rndm
CRC32CW .... 0001 0100 .... .... 0010 0100 .... @rndm

# Miscellaneous instructions

%sysm 8:1 16:4
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7 changes: 7 additions & 0 deletions target/arm/t32.decode
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Expand Up @@ -172,6 +172,13 @@ QSUB 1111 1010 1000 .... 1111 .... 1010 .... @rndm
QDADD 1111 1010 1000 .... 1111 .... 1001 .... @rndm
QDSUB 1111 1010 1000 .... 1111 .... 1011 .... @rndm

CRC32B 1111 1010 1100 .... 1111 .... 1000 .... @rndm
CRC32H 1111 1010 1100 .... 1111 .... 1001 .... @rndm
CRC32W 1111 1010 1100 .... 1111 .... 1010 .... @rndm
CRC32CB 1111 1010 1101 .... 1111 .... 1000 .... @rndm
CRC32CH 1111 1010 1101 .... 1111 .... 1001 .... @rndm
CRC32CW 1111 1010 1101 .... 1111 .... 1010 .... @rndm

# Branches and miscellaneous control

%msr_sysm 4:1 8:4
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121 changes: 56 additions & 65 deletions target/arm/translate.c
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Expand Up @@ -8320,6 +8320,57 @@ static bool trans_MSR_imm(DisasContext *s, arg_MSR_imm *a)
return true;
}

/*
* Cyclic Redundancy Check
*/

static bool op_crc32(DisasContext *s, arg_rrr *a, bool c, MemOp sz)
{
TCGv_i32 t1, t2, t3;

if (!dc_isar_feature(aa32_crc32, s)) {
return false;
}

t1 = load_reg(s, a->rn);
t2 = load_reg(s, a->rm);
switch (sz) {
case MO_8:
gen_uxtb(t2);
break;
case MO_16:
gen_uxth(t2);
break;
case MO_32:
break;
default:
g_assert_not_reached();
}
t3 = tcg_const_i32(1 << sz);
if (c) {
gen_helper_crc32c(t1, t1, t2, t3);
} else {
gen_helper_crc32(t1, t1, t2, t3);
}
tcg_temp_free_i32(t2);
tcg_temp_free_i32(t3);
store_reg(s, a->rd, t1);
return true;
}

#define DO_CRC32(NAME, c, sz) \
static bool trans_##NAME(DisasContext *s, arg_rrr *a) \
{ return op_crc32(s, a, c, sz); }

DO_CRC32(CRC32B, false, MO_8)
DO_CRC32(CRC32H, false, MO_16)
DO_CRC32(CRC32W, false, MO_32)
DO_CRC32(CRC32CB, true, MO_8)
DO_CRC32(CRC32CH, true, MO_16)
DO_CRC32(CRC32CW, true, MO_32)

#undef DO_CRC32

/*
* Miscellaneous instructions
*/
Expand Down Expand Up @@ -8735,39 +8786,9 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
gen_bx(s, tmp);
break;
case 0x4:
{
/* crc32/crc32c */
uint32_t c = extract32(insn, 8, 4);

/* Check this CPU supports ARMv8 CRC instructions.
* op1 == 3 is UNPREDICTABLE but handle as UNDEFINED.
* Bits 8, 10 and 11 should be zero.
*/
if (!dc_isar_feature(aa32_crc32, s) || op1 == 0x3 || (c & 0xd) != 0) {
goto illegal_op;
}

rn = extract32(insn, 16, 4);
rd = extract32(insn, 12, 4);

tmp = load_reg(s, rn);
tmp2 = load_reg(s, rm);
if (op1 == 0) {
tcg_gen_andi_i32(tmp2, tmp2, 0xff);
} else if (op1 == 1) {
tcg_gen_andi_i32(tmp2, tmp2, 0xffff);
}
tmp3 = tcg_const_i32(1 << op1);
if (c & 0x2) {
gen_helper_crc32c(tmp, tmp, tmp2, tmp3);
} else {
gen_helper_crc32(tmp, tmp, tmp2, tmp3);
}
tcg_temp_free_i32(tmp2);
tcg_temp_free_i32(tmp3);
store_reg(s, rd, tmp);
break;
}
/* crc32 */
/* All done in decodetree. Illegal ops reach here. */
goto illegal_op;
case 0x5:
/* Saturating addition and subtraction. */
/* All done in decodetree. Reach here for illegal ops. */
Expand Down Expand Up @@ -10216,16 +10237,13 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
goto illegal_op;
}
break;
case 0x20: /* crc32/crc32c */
case 0x20: /* crc32/crc32c, in decodetree */
case 0x21:
case 0x22:
case 0x28:
case 0x29:
case 0x2a:
if (!dc_isar_feature(aa32_crc32, s)) {
goto illegal_op;
}
break;
goto illegal_op;
default:
goto illegal_op;
}
Expand Down Expand Up @@ -10254,33 +10272,6 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
case 0x18: /* clz */
tcg_gen_clzi_i32(tmp, tmp, 32);
break;
case 0x20:
case 0x21:
case 0x22:
case 0x28:
case 0x29:
case 0x2a:
{
/* crc32/crc32c */
uint32_t sz = op & 0x3;
uint32_t c = op & 0x8;

tmp2 = load_reg(s, rm);
if (sz == 0) {
tcg_gen_andi_i32(tmp2, tmp2, 0xff);
} else if (sz == 1) {
tcg_gen_andi_i32(tmp2, tmp2, 0xffff);
}
tmp3 = tcg_const_i32(1 << sz);
if (c) {
gen_helper_crc32c(tmp, tmp, tmp2, tmp3);
} else {
gen_helper_crc32(tmp, tmp, tmp2, tmp3);
}
tcg_temp_free_i32(tmp2);
tcg_temp_free_i32(tmp3);
break;
}
default:
g_assert_not_reached();
}
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