target/riscv: fix a typo with interrupt names

Interrupt names have been swapped in 205377f and do not follow IRQ_*_EXT definition order. Signed-off-by: Emmanuel Blot <emmanuel.blot@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210421133236.11323-1-emmanuel.blot@sifive.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
qemu · May 11, 2021 · 6cfcf77 · 6cfcf77
1 parent 3a7f775
commit 6cfcf77
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
@@ -88,8 +88,8 @@ const char * const riscv_intr_names[] = {
     "vs_timer",
     "m_timer",
     "u_external",
+    "s_external",
     "vs_external",
-    "h_external",
     "m_external",
     "reserved",
     "reserved",