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Merge tag 'pull-ppc-20230804' of https://gitlab.com/danielhb/qemu int…
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…o staging

ppc patch queue for 2023-08-04:

This queue contains target/ppc register and VRMA fixes for 8.1. pegasos2
fixes are also included.

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# gpg: Signature made Fri 04 Aug 2023 08:26:26 AM PDT
# gpg:                using EDDSA key 17EBFF9923D01800AF2838193CD9CA96DE033164
# gpg:                issuer "danielhb413@gmail.com"
# gpg: Good signature from "Daniel Henrique Barboza <danielhb413@gmail.com>" [unknown]
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# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 17EB FF99 23D0 1800 AF28  3819 3CD9 CA96 DE03 3164

* tag 'pull-ppc-20230804' of https://gitlab.com/danielhb/qemu:
  target/ppc: Fix VRMA page size for ISA v3.0
  target/ppc: Fix pending HDEC when entering PM state
  target/ppc: Implement ASDR register for ISA v3.0 for HPT
  ppc/pegasos2: Fix reg property of 64 bit BARs in device tree
  ppc/pegasos2: Fix naming of device tree nodes
  ppc/pegasos2: Fix reg property of ROM BARs
  ppc/pegasos2: Fix reset state of USB functions

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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@rth7680
rth7680 committed Aug 4, 2023
2 parents c26d005 + 0e2a3ec commit 71934cf
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Showing 4 changed files with 88 additions and 19 deletions.
24 changes: 22 additions & 2 deletions hw/ppc/pegasos2.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -324,9 +324,13 @@ static void pegasos2_machine_reset(MachineState *machine, ShutdownCause reason)

pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 2) << 8) |
PCI_INTERRUPT_LINE, 2, 0x409);
pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 2) << 8) |
PCI_COMMAND, 2, 0x7);

pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 3) << 8) |
PCI_INTERRUPT_LINE, 2, 0x409);
pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 3) << 8) |
PCI_COMMAND, 2, 0x7);

pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 4) << 8) |
PCI_INTERRUPT_LINE, 2, 0x9);
Expand Down Expand Up @@ -735,6 +739,13 @@ static void add_pci_device(PCIBus *bus, PCIDevice *d, void *opaque)
pci_get_word(&d->config[PCI_VENDOR_ID]),
pci_get_word(&d->config[PCI_DEVICE_ID]));

if (pci_get_word(&d->config[PCI_CLASS_DEVICE]) ==
PCI_CLASS_NETWORK_ETHERNET) {
name = "ethernet";
} else if (pci_get_word(&d->config[PCI_CLASS_DEVICE]) >> 8 ==
PCI_BASE_CLASS_DISPLAY) {
name = "display";
}
for (i = 0; device_map[i].id; i++) {
if (!strcmp(pn, device_map[i].id)) {
name = device_map[i].name;
Expand Down Expand Up @@ -762,11 +773,19 @@ static void add_pci_device(PCIBus *bus, PCIDevice *d, void *opaque)
if (!d->io_regions[i].size) {
continue;
}
cells[j] = cpu_to_be32(d->devfn << 8 | (PCI_BASE_ADDRESS_0 + i * 4));
cells[j] = PCI_BASE_ADDRESS_0 + i * 4;
if (cells[j] == 0x28) {
cells[j] = 0x30;
}
cells[j] = cpu_to_be32(d->devfn << 8 | cells[j]);
if (d->io_regions[i].type & PCI_BASE_ADDRESS_SPACE_IO) {
cells[j] |= cpu_to_be32(1 << 24);
} else {
cells[j] |= cpu_to_be32(2 << 24);
if (d->io_regions[i].type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
cells[j] |= cpu_to_be32(3 << 24);
} else {
cells[j] |= cpu_to_be32(2 << 24);
}
if (d->io_regions[i].type & PCI_BASE_ADDRESS_MEM_PREFETCH) {
cells[j] |= cpu_to_be32(4 << 28);
}
Expand Down Expand Up @@ -921,6 +940,7 @@ static void *build_fdt(MachineState *machine, int *fdt_size)
qemu_fdt_setprop_cell(fdt, "/rtas", "rtas-display-device", 0);
qemu_fdt_setprop_cell(fdt, "/rtas", "rtas-size", 20);
qemu_fdt_setprop_cell(fdt, "/rtas", "rtas-version", 1);
qemu_fdt_setprop_string(fdt, "/rtas", "name", "rtas");

/* cpus */
qemu_fdt_add_subnode(fdt, "/cpus");
Expand Down
6 changes: 6 additions & 0 deletions target/ppc/excp_helper.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -2685,6 +2685,12 @@ void helper_pminsn(CPUPPCState *env, uint32_t insn)
env->resume_as_sreset = (insn != PPC_PM_STOP) ||
(env->spr[SPR_PSSCR] & PSSCR_EC);

/* HDECR is not to wake from PM state, it may have already fired */
if (env->resume_as_sreset) {
PowerPCCPU *cpu = env_archcpu(env);
ppc_set_irq(cpu, PPC_INTERRUPT_HDECR, 0);
}

ppc_maybe_interrupt(env);
}
#endif /* defined(TARGET_PPC64) */
Expand Down
72 changes: 55 additions & 17 deletions target/ppc/mmu-hash64.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -770,7 +770,8 @@ static bool ppc_hash64_use_vrma(CPUPPCState *env)
}
}

static void ppc_hash64_set_isi(CPUState *cs, int mmu_idx, uint64_t error_code)
static void ppc_hash64_set_isi(CPUState *cs, int mmu_idx, uint64_t slb_vsid,
uint64_t error_code)
{
CPUPPCState *env = &POWERPC_CPU(cs)->env;
bool vpm;
Expand All @@ -782,13 +783,15 @@ static void ppc_hash64_set_isi(CPUState *cs, int mmu_idx, uint64_t error_code)
}
if (vpm && !mmuidx_hv(mmu_idx)) {
cs->exception_index = POWERPC_EXCP_HISI;
env->spr[SPR_ASDR] = slb_vsid;
} else {
cs->exception_index = POWERPC_EXCP_ISI;
}
env->error_code = error_code;
}

static void ppc_hash64_set_dsi(CPUState *cs, int mmu_idx, uint64_t dar, uint64_t dsisr)
static void ppc_hash64_set_dsi(CPUState *cs, int mmu_idx, uint64_t slb_vsid,
uint64_t dar, uint64_t dsisr)
{
CPUPPCState *env = &POWERPC_CPU(cs)->env;
bool vpm;
Expand All @@ -802,6 +805,7 @@ static void ppc_hash64_set_dsi(CPUState *cs, int mmu_idx, uint64_t dar, uint64_t
cs->exception_index = POWERPC_EXCP_HDSI;
env->spr[SPR_HDAR] = dar;
env->spr[SPR_HDSISR] = dsisr;
env->spr[SPR_ASDR] = slb_vsid;
} else {
cs->exception_index = POWERPC_EXCP_DSI;
env->spr[SPR_DAR] = dar;
Expand Down Expand Up @@ -870,12 +874,46 @@ static target_ulong rmls_limit(PowerPCCPU *cpu)
return rma_sizes[rmls];
}

static int build_vrma_slbe(PowerPCCPU *cpu, ppc_slb_t *slb)
/* Return the LLP in SLB_VSID format */
static uint64_t get_vrma_llp(PowerPCCPU *cpu)
{
CPUPPCState *env = &cpu->env;
target_ulong lpcr = env->spr[SPR_LPCR];
uint32_t vrmasd = (lpcr & LPCR_VRMASD) >> LPCR_VRMASD_SHIFT;
target_ulong vsid = SLB_VSID_VRMA | ((vrmasd << 4) & SLB_VSID_LLP_MASK);
uint64_t llp;

if (env->mmu_model == POWERPC_MMU_3_00) {
ppc_v3_pate_t pate;
uint64_t ps, l, lp;

/*
* ISA v3.0 removes the LPCR[VRMASD] field and puts the VRMA base
* page size (L||LP equivalent) in the PS field in the HPT partition
* table entry.
*/
if (!ppc64_v3_get_pate(cpu, cpu->env.spr[SPR_LPIDR], &pate)) {
error_report("Bad VRMA with no partition table entry");
return 0;
}
ps = PATE0_GET_PS(pate.dw0);
/* PS has L||LP in 3 consecutive bits, put them into SLB LLP format */
l = (ps >> 2) & 0x1;
lp = ps & 0x3;
llp = (l << SLB_VSID_L_SHIFT) | (lp << SLB_VSID_LP_SHIFT);

} else {
uint64_t lpcr = env->spr[SPR_LPCR];
target_ulong vrmasd = (lpcr & LPCR_VRMASD) >> LPCR_VRMASD_SHIFT;

/* VRMASD LLP matches SLB format, just shift and mask it */
llp = (vrmasd << SLB_VSID_LP_SHIFT) & SLB_VSID_LLP_MASK;
}

return llp;
}

static int build_vrma_slbe(PowerPCCPU *cpu, ppc_slb_t *slb)
{
uint64_t llp = get_vrma_llp(cpu);
target_ulong vsid = SLB_VSID_VRMA | llp;
int i;

for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) {
Expand All @@ -893,8 +931,7 @@ static int build_vrma_slbe(PowerPCCPU *cpu, ppc_slb_t *slb)
}
}

error_report("Bad page size encoding in LPCR[VRMASD]; LPCR=0x"
TARGET_FMT_lx, lpcr);
error_report("Bad VRMA page size encoding 0x" TARGET_FMT_lx, llp);

return -1;
}
Expand Down Expand Up @@ -963,13 +1000,13 @@ bool ppc_hash64_xlate(PowerPCCPU *cpu, vaddr eaddr, MMUAccessType access_type,
}
switch (access_type) {
case MMU_INST_FETCH:
ppc_hash64_set_isi(cs, mmu_idx, SRR1_PROTFAULT);
ppc_hash64_set_isi(cs, mmu_idx, 0, SRR1_PROTFAULT);
break;
case MMU_DATA_LOAD:
ppc_hash64_set_dsi(cs, mmu_idx, eaddr, DSISR_PROTFAULT);
ppc_hash64_set_dsi(cs, mmu_idx, 0, eaddr, DSISR_PROTFAULT);
break;
case MMU_DATA_STORE:
ppc_hash64_set_dsi(cs, mmu_idx, eaddr,
ppc_hash64_set_dsi(cs, mmu_idx, 0, eaddr,
DSISR_PROTFAULT | DSISR_ISSTORE);
break;
default:
Expand Down Expand Up @@ -1022,7 +1059,7 @@ bool ppc_hash64_xlate(PowerPCCPU *cpu, vaddr eaddr, MMUAccessType access_type,
/* 3. Check for segment level no-execute violation */
if (access_type == MMU_INST_FETCH && (slb->vsid & SLB_VSID_N)) {
if (guest_visible) {
ppc_hash64_set_isi(cs, mmu_idx, SRR1_NOEXEC_GUARD);
ppc_hash64_set_isi(cs, mmu_idx, slb->vsid, SRR1_NOEXEC_GUARD);
}
return false;
}
Expand All @@ -1035,13 +1072,14 @@ bool ppc_hash64_xlate(PowerPCCPU *cpu, vaddr eaddr, MMUAccessType access_type,
}
switch (access_type) {
case MMU_INST_FETCH:
ppc_hash64_set_isi(cs, mmu_idx, SRR1_NOPTE);
ppc_hash64_set_isi(cs, mmu_idx, slb->vsid, SRR1_NOPTE);
break;
case MMU_DATA_LOAD:
ppc_hash64_set_dsi(cs, mmu_idx, eaddr, DSISR_NOPTE);
ppc_hash64_set_dsi(cs, mmu_idx, slb->vsid, eaddr, DSISR_NOPTE);
break;
case MMU_DATA_STORE:
ppc_hash64_set_dsi(cs, mmu_idx, eaddr, DSISR_NOPTE | DSISR_ISSTORE);
ppc_hash64_set_dsi(cs, mmu_idx, slb->vsid, eaddr,
DSISR_NOPTE | DSISR_ISSTORE);
break;
default:
g_assert_not_reached();
Expand Down Expand Up @@ -1075,7 +1113,7 @@ bool ppc_hash64_xlate(PowerPCCPU *cpu, vaddr eaddr, MMUAccessType access_type,
if (PAGE_EXEC & ~amr_prot) {
srr1 |= SRR1_IAMR; /* Access violates virt pg class key prot */
}
ppc_hash64_set_isi(cs, mmu_idx, srr1);
ppc_hash64_set_isi(cs, mmu_idx, slb->vsid, srr1);
} else {
int dsisr = 0;
if (need_prot & ~pp_prot) {
Expand All @@ -1087,7 +1125,7 @@ bool ppc_hash64_xlate(PowerPCCPU *cpu, vaddr eaddr, MMUAccessType access_type,
if (need_prot & ~amr_prot) {
dsisr |= DSISR_AMR;
}
ppc_hash64_set_dsi(cs, mmu_idx, eaddr, dsisr);
ppc_hash64_set_dsi(cs, mmu_idx, slb->vsid, eaddr, dsisr);
}
return false;
}
Expand Down
5 changes: 5 additions & 0 deletions target/ppc/mmu-hash64.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -41,8 +41,10 @@ void ppc_hash64_finalize(PowerPCCPU *cpu);
#define SLB_VSID_KP 0x0000000000000400ULL
#define SLB_VSID_N 0x0000000000000200ULL /* no-execute */
#define SLB_VSID_L 0x0000000000000100ULL
#define SLB_VSID_L_SHIFT PPC_BIT_NR(55)
#define SLB_VSID_C 0x0000000000000080ULL /* class */
#define SLB_VSID_LP 0x0000000000000030ULL
#define SLB_VSID_LP_SHIFT PPC_BIT_NR(59)
#define SLB_VSID_ATTR 0x0000000000000FFFULL
#define SLB_VSID_LLP_MASK (SLB_VSID_L | SLB_VSID_LP)
#define SLB_VSID_4K 0x0000000000000000ULL
Expand All @@ -58,6 +60,9 @@ void ppc_hash64_finalize(PowerPCCPU *cpu);
#define SDR_64_HTABSIZE 0x000000000000001FULL

#define PATE0_HTABORG 0x0FFFFFFFFFFC0000ULL
#define PATE0_PS PPC_BITMASK(56, 58)
#define PATE0_GET_PS(dw0) (((dw0) & PATE0_PS) >> PPC_BIT_NR(58))

#define HPTES_PER_GROUP 8
#define HASH_PTE_SIZE_64 16
#define HASH_PTEG_SIZE_64 (HASH_PTE_SIZE_64 * HPTES_PER_GROUP)
Expand Down

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