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Merge tag 'pull-target-arm-20230704' of https://git.linaro.org/people…
…/pmaydell/qemu-arm into staging target-arm queue: * Add raw_writes ops for register whose write induce TLB maintenance * hw/arm/sbsa-ref: use XHCI to replace EHCI * Avoid splitting Zregs across lines in dump * Dump ZA[] when active * Fix SME full tile indexing * Handle IC IVAU to improve compatibility with JITs * xlnx-canfd-test: Fix code coverity issues * gdbstub: Guard M-profile code with CONFIG_TCG * allwinner-sramc: Set class_size * target/xtensa: Assert that interrupt level is within bounds # -----BEGIN PGP SIGNATURE----- # # iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmSkSnEZHHBldGVyLm1h # eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3txnD/9AOIGrr03CKG1RLitM+6b2 # dNOx//iFpRVIOja5PmENQ8eNOF9MXHiQeJ5Xd83ldnSsuV3wvXRiQ0YfJCoFRrL3 # 3uklz61SL3S5/aQ6uvCiewE+nORX39kl+2CUzsczYOTSkjc/gzsUxaojPlP7aXqJ # n2OaDLLuXkW3P19L/TZulTbzEg80p5Xmpr7RwaYndxoQlMTeyr80CKoJ76M8TZP0 # hTciij5nlBjUTLGxejD1BCrhtYwa+HNkYTRrDUPVZogIYpIJeD90uI9dsORpT0Df # zZLxCW+xPtm/057PSDbYM3QLX3nQN09WmciWrv5rsyk4JU49v2NLaYeNWV7SXi/V # FpNwA67M0pm7f1fep9yOCjVt51iGDONweQkqRIz+ok40FsoKbslKQuFhuXxl4LE3 # OLVLE26hu6cEVsMd0I1zipvDzyhuWk2lw+Qpi8zxSGoKaXYTK8oq8YTJ2lZspC8K # EXAaDipr9gtWpOGHLQbX30fY/+2KX29g9Ih2FXjN5p5/UlcyJZKRyYI/jMvCUHRm # f8k7vGlx8+s8hRoa6stXXbbFXoJbgywMd6B5sXMTVXnRvTLN3im4QQlyHDbHhrg9 # qoksSQ5hGG3og29drDKXIkoMxn2m71DXmriPweLp2MRqkhD4DMQS1YGjeJSxSrZe # u+Z4cusrj1nzwSQK98j2UA== # =vtOk # -----END PGP SIGNATURE----- # gpg: Signature made Tue 04 Jul 2023 06:36:01 PM CEST # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [full] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full] # gpg: aka "Peter Maydell <peter@archaic.org.uk>" [unknown] * tag 'pull-target-arm-20230704' of https://git.linaro.org/people/pmaydell/qemu-arm: target/xtensa: Assert that interrupt level is within bounds hw: arm: allwinner-sramc: Set class_size target/arm: gdbstub: Guard M-profile code with CONFIG_TCG tests/qtest: xlnx-canfd-test: Fix code coverity issues tests/tcg/aarch64: Add testcases for IC IVAU and dual-mapped code target/arm: Handle IC IVAU to improve compatibility with JITs target/arm: Fix SME full tile indexing target/arm: Dump ZA[] when active target/arm: Avoid splitting Zregs across lines in dump hw/arm/sbsa-ref: use XHCI to replace EHCI target/arm: Add raw_writes ops for register whose write induce TLB maintenance Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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