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Merge tag 'pull-riscv-to-apply-20220429' of github.com:alistair23/qem…
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…u into staging

Second RISC-V PR for QEMU 7.1

 * Improve device tree generation
 * Support configuarable marchid, mvendorid, mipid CSR values
 * Add support for the Zbkb, Zbkc, Zbkx, Zknd/Zkne, Zknh, Zksed/Zksh and Zkr extensions
 * Fix incorrect PTE merge in walk_pte
 * Add TPM support to the virt board

# -----BEGIN PGP SIGNATURE-----
#
# iQEzBAABCAAdFiEE9sSsRtSTSGjTuM6PIeENKd+XcFQFAmJraeUACgkQIeENKd+X
# cFRLjgf9GFmxPhOC8cb7wN6xsiJIiVmmcTGHKfUgFTAIR2KLOEm2fo28YNrgewok
# Hi7FBHLhYKEivz70GFVg7q6oJlqhYx8fL4AB0sodTetIcJGQPQgz8zN7ZD8utnzA
# d6n7ZruyW5IuUqCBUcsHNqBHxoYanR88rr6YpxU+nSz0WALYRgQliXm5zqK1rwNc
# v8HpLHyN7JUmAQmJ1U6Uc6IFi/cFn9e/Hs/uRMevKov2nCTxeeAq5G2r8JGKpx35
# VRid91dcWbGiRY1xHWqnl/0WZxl8Jp4av1e5NDbXfwYPvwiI2fza5KFasp2S38yR
# VvnUcI+p73qclCF7LkfL9c//xQT1iA==
# =Xkoz
# -----END PGP SIGNATURE-----
# gpg: Signature made Thu 28 Apr 2022 09:30:29 PM PDT
# gpg:                using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [undefined]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: F6C4 AC46 D493 4868 D3B8  CE8F 21E1 0D29 DF97 7054

* tag 'pull-riscv-to-apply-20220429' of github.com:alistair23/qemu: (25 commits)
  hw/riscv: Enable TPM backends
  hw/riscv: virt: Add device plug support
  hw/riscv: virt: Add support for generating platform FDT entries
  hw/riscv: virt: Create a platform bus
  hw/core: Move the ARM sysbus-fdt to core
  hw/riscv: virt: Add a machine done notifier
  target/riscv: add scalar crypto related extenstion strings to isa_string
  target/riscv: Fix incorrect PTE merge in walk_pte
  target/riscv: rvk: expose zbk* and zk* properties
  disas/riscv.c: rvk: add disas support for Zbk* and Zk* instructions
  target/riscv: rvk: add CSR support for Zkr
  target/riscv: rvk: add support for zksed/zksh extension
  target/riscv: rvk: add support for sha512 related instructions for RV64 in zknh extension
  target/riscv: rvk: add support for sha512 related instructions for RV32 in zknh extension
  target/riscv: rvk: add support for sha256 related instructions in zknh extension
  target/riscv: rvk: add support for zkne/zknd extension in RV64
  target/riscv: rvk: add support for zknd/zkne extension in RV32
  crypto: move sm4_sbox from target/arm
  target/riscv: rvk: add support for zbkx extension
  target/riscv: rvk: add support for zbkc extension
  ...

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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@rth7680
rth7680 committed Apr 29, 2022
2 parents f228336 + 325b7c4 commit 7313408
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Showing 33 changed files with 1,682 additions and 199 deletions.
1 change: 1 addition & 0 deletions crypto/meson.build
View file
Expand Up @@ -42,6 +42,7 @@ if have_afalg
endif
crypto_ss.add(when: gnutls, if_true: files('tls-cipher-suites.c'))

util_ss.add(files('sm4.c'))
util_ss.add(files('aes.c'))
util_ss.add(files('init.c'))
if gnutls.found()
Expand Down
49 changes: 49 additions & 0 deletions crypto/sm4.c
View file
@@ -0,0 +1,49 @@
/*
* QEMU crypto sm4 support
*
* Copyright (C) 2013 - 2018 Linaro Ltd <ard.biesheuvel@linaro.org>
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2.1 of the License, or (at your option) any later version.
*/

#include "qemu/osdep.h"
#include "crypto/sm4.h"

uint8_t const sm4_sbox[] = {
0xd6, 0x90, 0xe9, 0xfe, 0xcc, 0xe1, 0x3d, 0xb7,
0x16, 0xb6, 0x14, 0xc2, 0x28, 0xfb, 0x2c, 0x05,
0x2b, 0x67, 0x9a, 0x76, 0x2a, 0xbe, 0x04, 0xc3,
0xaa, 0x44, 0x13, 0x26, 0x49, 0x86, 0x06, 0x99,
0x9c, 0x42, 0x50, 0xf4, 0x91, 0xef, 0x98, 0x7a,
0x33, 0x54, 0x0b, 0x43, 0xed, 0xcf, 0xac, 0x62,
0xe4, 0xb3, 0x1c, 0xa9, 0xc9, 0x08, 0xe8, 0x95,
0x80, 0xdf, 0x94, 0xfa, 0x75, 0x8f, 0x3f, 0xa6,
0x47, 0x07, 0xa7, 0xfc, 0xf3, 0x73, 0x17, 0xba,
0x83, 0x59, 0x3c, 0x19, 0xe6, 0x85, 0x4f, 0xa8,
0x68, 0x6b, 0x81, 0xb2, 0x71, 0x64, 0xda, 0x8b,
0xf8, 0xeb, 0x0f, 0x4b, 0x70, 0x56, 0x9d, 0x35,
0x1e, 0x24, 0x0e, 0x5e, 0x63, 0x58, 0xd1, 0xa2,
0x25, 0x22, 0x7c, 0x3b, 0x01, 0x21, 0x78, 0x87,
0xd4, 0x00, 0x46, 0x57, 0x9f, 0xd3, 0x27, 0x52,
0x4c, 0x36, 0x02, 0xe7, 0xa0, 0xc4, 0xc8, 0x9e,
0xea, 0xbf, 0x8a, 0xd2, 0x40, 0xc7, 0x38, 0xb5,
0xa3, 0xf7, 0xf2, 0xce, 0xf9, 0x61, 0x15, 0xa1,
0xe0, 0xae, 0x5d, 0xa4, 0x9b, 0x34, 0x1a, 0x55,
0xad, 0x93, 0x32, 0x30, 0xf5, 0x8c, 0xb1, 0xe3,
0x1d, 0xf6, 0xe2, 0x2e, 0x82, 0x66, 0xca, 0x60,
0xc0, 0x29, 0x23, 0xab, 0x0d, 0x53, 0x4e, 0x6f,
0xd5, 0xdb, 0x37, 0x45, 0xde, 0xfd, 0x8e, 0x2f,
0x03, 0xff, 0x6a, 0x72, 0x6d, 0x6c, 0x5b, 0x51,
0x8d, 0x1b, 0xaf, 0x92, 0xbb, 0xdd, 0xbc, 0x7f,
0x11, 0xd9, 0x5c, 0x41, 0x1f, 0x10, 0x5a, 0xd8,
0x0a, 0xc1, 0x31, 0x88, 0xa5, 0xcd, 0x7b, 0xbd,
0x2d, 0x74, 0xd0, 0x12, 0xb8, 0xe5, 0xb4, 0xb0,
0x89, 0x69, 0x97, 0x4a, 0x0c, 0x96, 0x77, 0x7e,
0x65, 0xb9, 0xf1, 0x09, 0xc5, 0x6e, 0xc6, 0x84,
0x18, 0xf0, 0x7d, 0xec, 0x3a, 0xdc, 0x4d, 0x20,
0x79, 0xee, 0x5f, 0x3e, 0xd7, 0xcb, 0x39, 0x48,
};

173 changes: 172 additions & 1 deletion disas/riscv.c
View file
Expand Up @@ -156,6 +156,8 @@ typedef enum {
rv_codec_css_swsp,
rv_codec_css_sdsp,
rv_codec_css_sqsp,
rv_codec_k_bs,
rv_codec_k_rnum,
} rv_codec;

typedef enum {
Expand Down Expand Up @@ -521,6 +523,43 @@ typedef enum {
rv_op_bclr = 359,
rv_op_binv = 360,
rv_op_bext = 361,
rv_op_aes32esmi = 362,
rv_op_aes32esi = 363,
rv_op_aes32dsmi = 364,
rv_op_aes32dsi = 365,
rv_op_aes64ks1i = 366,
rv_op_aes64ks2 = 367,
rv_op_aes64im = 368,
rv_op_aes64esm = 369,
rv_op_aes64es = 370,
rv_op_aes64dsm = 371,
rv_op_aes64ds = 372,
rv_op_sha256sig0 = 373,
rv_op_sha256sig1 = 374,
rv_op_sha256sum0 = 375,
rv_op_sha256sum1 = 376,
rv_op_sha512sig0 = 377,
rv_op_sha512sig1 = 378,
rv_op_sha512sum0 = 379,
rv_op_sha512sum1 = 380,
rv_op_sha512sum0r = 381,
rv_op_sha512sum1r = 382,
rv_op_sha512sig0l = 383,
rv_op_sha512sig0h = 384,
rv_op_sha512sig1l = 385,
rv_op_sha512sig1h = 386,
rv_op_sm3p0 = 387,
rv_op_sm3p1 = 388,
rv_op_sm4ed = 389,
rv_op_sm4ks = 390,
rv_op_brev8 = 391,
rv_op_pack = 392,
rv_op_packh = 393,
rv_op_packw = 394,
rv_op_unzip = 395,
rv_op_zip = 396,
rv_op_xperm4 = 397,
rv_op_xperm8 = 398,
} rv_op;

/* structures */
Expand All @@ -540,6 +579,8 @@ typedef struct {
uint8_t succ;
uint8_t aq;
uint8_t rl;
uint8_t bs;
uint8_t rnum;
} rv_decode;

typedef struct {
Expand Down Expand Up @@ -615,6 +656,8 @@ static const char rv_freg_name_sym[32][5] = {
#define rv_fmt_rd_rs2 "O\t0,2"
#define rv_fmt_rs1_offset "O\t1,o"
#define rv_fmt_rs2_offset "O\t2,o"
#define rv_fmt_rs1_rs2_bs "O\t1,2,b"
#define rv_fmt_rd_rs1_rnum "O\t0,1,n"

/* pseudo-instruction constraints */

Expand Down Expand Up @@ -766,6 +809,7 @@ static const rv_comp_data rvcp_csrrw[] = {
{ rv_op_illegal, NULL }
};


static const rv_comp_data rvcp_csrrs[] = {
{ rv_op_rdcycle, rvcc_rdcycle },
{ rv_op_rdtime, rvcc_rdtime },
Expand Down Expand Up @@ -1203,6 +1247,43 @@ const rv_opcode_data opcode_data[] = {
{ "bclr", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
{ "binv", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
{ "bext", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
{ "aes32esmi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 },
{ "aes32esi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 },
{ "aes32dsmi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 },
{ "aes32dsi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 },
{ "aes64ks1i", rv_codec_k_rnum, rv_fmt_rd_rs1_rnum, NULL, 0, 0, 0 },
{ "aes64ks2", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
{ "aes64im", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
{ "aes64esm", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
{ "aes64es", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
{ "aes64dsm", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
{ "aes64ds", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
{ "sha256sig0", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
{ "sha256sig1", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
{ "sha256sum0", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
{ "sha256sum1", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
{ "sha512sig0", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
{ "sha512sig1", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
{ "sha512sum0", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
{ "sha512sum1", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
{ "sha512sum0r", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
{ "sha512sum1r", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
{ "sha512sig0l", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
{ "sha512sig0h", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
{ "sha512sig1l", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
{ "sha512sig1h", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
{ "sm3p0", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
{ "sm3p1", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
{ "sm4ed", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 },
{ "sm4ks", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 },
{ "brev8", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
{ "pack", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
{ "packh", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
{ "packw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
{ "unzip", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
{ "zip", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
{ "xperm4", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
{ "xperm8", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }
};

/* CSR names */
Expand All @@ -1216,6 +1297,7 @@ static const char *csr_name(int csrno)
case 0x0003: return "fcsr";
case 0x0004: return "uie";
case 0x0005: return "utvec";
case 0x0015: return "seed";
case 0x0040: return "uscratch";
case 0x0041: return "uepc";
case 0x0042: return "ucause";
Expand Down Expand Up @@ -1594,7 +1676,36 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
case 1:
switch (((inst >> 27) & 0b11111)) {
case 0b00000: op = rv_op_slli; break;
case 0b00001:
switch (((inst >> 20) & 0b1111111)) {
case 0b0001111: op = rv_op_zip; break;
}
break;
case 0b00010:
switch (((inst >> 20) & 0b1111111)) {
case 0b0000000: op = rv_op_sha256sum0; break;
case 0b0000001: op = rv_op_sha256sum1; break;
case 0b0000010: op = rv_op_sha256sig0; break;
case 0b0000011: op = rv_op_sha256sig1; break;
case 0b0000100: op = rv_op_sha512sum0; break;
case 0b0000101: op = rv_op_sha512sum1; break;
case 0b0000110: op = rv_op_sha512sig0; break;
case 0b0000111: op = rv_op_sha512sig1; break;
case 0b0001000: op = rv_op_sm3p0; break;
case 0b0001001: op = rv_op_sm3p1; break;
}
break;
case 0b00101: op = rv_op_bseti; break;
case 0b00110:
switch (((inst >> 20) & 0b1111111)) {
case 0b0000000: op = rv_op_aes64im; break;
default:
if (((inst >> 24) & 0b0111) == 0b001) {
op = rv_op_aes64ks1i;
}
break;
}
break;
case 0b01001: op = rv_op_bclri; break;
case 0b01101: op = rv_op_binvi; break;
case 0b01100:
Expand All @@ -1615,13 +1726,20 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
case 5:
switch (((inst >> 27) & 0b11111)) {
case 0b00000: op = rv_op_srli; break;
case 0b00001:
switch (((inst >> 20) & 0b1111111)) {
case 0b0001111: op = rv_op_unzip; break;
}
break;
case 0b00101: op = rv_op_orc_b; break;
case 0b01000: op = rv_op_srai; break;
case 0b01001: op = rv_op_bexti; break;
case 0b01100: op = rv_op_rori; break;
case 0b01101:
switch ((inst >> 20) & 0b1111111) {
case 0b0011000: op = rv_op_rev8; break;
case 0b0111000: op = rv_op_rev8; break;
case 0b0000111: op = rv_op_brev8; break;
}
break;
}
Expand Down Expand Up @@ -1742,8 +1860,11 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
case 36:
switch ((inst >> 20) & 0b11111) {
case 0: op = rv_op_zext_h; break;
default: op = rv_op_pack; break;
}
break;
case 39: op = rv_op_packh; break;

case 41: op = rv_op_clmul; break;
case 42: op = rv_op_clmulr; break;
case 43: op = rv_op_clmulh; break;
Expand All @@ -1755,16 +1876,37 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
case 132: op = rv_op_sh2add; break;
case 134: op = rv_op_sh3add; break;
case 161: op = rv_op_bset; break;
case 162: op = rv_op_xperm4; break;
case 164: op = rv_op_xperm8; break;
case 200: op = rv_op_aes64es; break;
case 216: op = rv_op_aes64esm; break;
case 232: op = rv_op_aes64ds; break;
case 248: op = rv_op_aes64dsm; break;
case 256: op = rv_op_sub; break;
case 260: op = rv_op_xnor; break;
case 261: op = rv_op_sra; break;
case 262: op = rv_op_orn; break;
case 263: op = rv_op_andn; break;
case 289: op = rv_op_bclr; break;
case 293: op = rv_op_bext; break;
case 320: op = rv_op_sha512sum0r; break;
case 328: op = rv_op_sha512sum1r; break;
case 336: op = rv_op_sha512sig0l; break;
case 344: op = rv_op_sha512sig1l; break;
case 368: op = rv_op_sha512sig0h; break;
case 376: op = rv_op_sha512sig1h; break;
case 385: op = rv_op_rol; break;
case 386: op = rv_op_ror; break;
case 389: op = rv_op_ror; break;
case 417: op = rv_op_binv; break;
case 504: op = rv_op_aes64ks2; break;
}
switch ((inst >> 25) & 0b0011111) {
case 17: op = rv_op_aes32esi; break;
case 19: op = rv_op_aes32esmi; break;
case 21: op = rv_op_aes32dsi; break;
case 23: op = rv_op_aes32dsmi; break;
case 24: op = rv_op_sm4ed; break;
case 26: op = rv_op_sm4ks; break;
}
break;
case 13: op = rv_op_lui; break;
Expand All @@ -1782,6 +1924,7 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
case 36:
switch ((inst >> 20) & 0b11111) {
case 0: op = rv_op_zext_h; break;
default: op = rv_op_packw; break;
}
break;
case 130: op = rv_op_sh1add_uw; break;
Expand Down Expand Up @@ -2374,6 +2517,16 @@ static uint32_t operand_cimmq(rv_inst inst)
((inst << 57) >> 62) << 6;
}

static uint32_t operand_bs(rv_inst inst)
{
return (inst << 32) >> 62;
}

static uint32_t operand_rnum(rv_inst inst)
{
return (inst << 40) >> 60;
}

/* decode operands */

static void decode_inst_operands(rv_decode *dec)
Expand Down Expand Up @@ -2653,6 +2806,16 @@ static void decode_inst_operands(rv_decode *dec)
dec->rs2 = operand_crs2(inst);
dec->imm = operand_cimmsqsp(inst);
break;
case rv_codec_k_bs:
dec->rs1 = operand_rs1(inst);
dec->rs2 = operand_rs2(inst);
dec->bs = operand_bs(inst);
break;
case rv_codec_k_rnum:
dec->rd = operand_rd(inst);
dec->rs1 = operand_rs1(inst);
dec->rnum = operand_rnum(inst);
break;
};
}

Expand Down Expand Up @@ -2812,6 +2975,14 @@ static void format_inst(char *buf, size_t buflen, size_t tab, rv_decode *dec)
case ')':
append(buf, ")", buflen);
break;
case 'b':
snprintf(tmp, sizeof(tmp), "%d", dec->bs);
append(buf, tmp, buflen);
break;
case 'n':
snprintf(tmp, sizeof(tmp), "%d", dec->rnum);
append(buf, tmp, buflen);
break;
case '0':
append(buf, rv_ireg_name_sym[dec->rd], buflen);
break;
Expand Down
20 changes: 20 additions & 0 deletions docs/system/riscv/virt.rst
View file
Expand Up @@ -162,3 +162,23 @@ The minimal QEMU commands to run U-Boot SPL are:
To test 32-bit U-Boot images, switch to use qemu-riscv32_smode_defconfig and
riscv32_spl_defconfig builds, and replace ``qemu-system-riscv64`` with
``qemu-system-riscv32`` in the command lines above to boot the 32-bit U-Boot.

Enabling TPM
------------

A TPM device can be connected to the virt board by following the steps below.

First launch the TPM emulator

swtpm socket --tpm2 -t -d --tpmstate dir=/tmp/tpm \
--ctrl type=unixio,path=swtpm-sock

Then launch QEMU with:

...
-chardev socket,id=chrtpm,path=swtpm-sock \
-tpmdev emulator,id=tpm0,chardev=chrtpm \
-device tpm-tis-device,tpmdev=tpm0

The TPM device can be seen in the memory tree and the generated device
tree and should be accessible from the guest software.
1 change: 0 additions & 1 deletion hw/arm/meson.build
View file
@@ -1,6 +1,5 @@
arm_ss = ss.source_set()
arm_ss.add(files('boot.c'), fdt)
arm_ss.add(when: 'CONFIG_PLATFORM_BUS', if_true: files('sysbus-fdt.c'))
arm_ss.add(when: 'CONFIG_ARM_VIRT', if_true: files('virt.c'))
arm_ss.add(when: 'CONFIG_ACPI', if_true: files('virt-acpi-build.c'))
arm_ss.add(when: 'CONFIG_DIGIC', if_true: files('digic_boards.c'))
Expand Down
2 changes: 1 addition & 1 deletion hw/arm/virt.c
View file
Expand Up @@ -56,7 +56,7 @@
#include "qemu/module.h"
#include "hw/pci-host/gpex.h"
#include "hw/virtio/virtio-pci.h"
#include "hw/arm/sysbus-fdt.h"
#include "hw/core/sysbus-fdt.h"
#include "hw/platform-bus.h"
#include "hw/qdev-properties.h"
#include "hw/arm/fdt.h"
Expand Down

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