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target/arm: Perform fpdp_v2 check first
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Shuffle the order of the checks so that we test the ISA
before we test anything else, such as the register arguments.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200224222232.13807-7-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@rth7680 @pm215
rth7680 authored and pm215 committed Feb 28, 2020
1 parent 7d63183 commit 799449a
Showing 1 changed file with 71 additions and 69 deletions.
140 changes: 71 additions & 69 deletions target/arm/translate-vfp.inc.c
View file
Expand Up @@ -200,13 +200,13 @@ static bool trans_VSEL(DisasContext *s, arg_VSEL *a)
return false;
}

/* UNDEF accesses to D16-D31 if they don't exist */
if (dp && !dc_isar_feature(aa32_simd_r32, s) &&
((a->vm | a->vn | a->vd) & 0x10)) {
if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}

if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) {
/* UNDEF accesses to D16-D31 if they don't exist */
if (dp && !dc_isar_feature(aa32_simd_r32, s) &&
((a->vm | a->vn | a->vd) & 0x10)) {
return false;
}

Expand Down Expand Up @@ -333,13 +333,13 @@ static bool trans_VMINMAXNM(DisasContext *s, arg_VMINMAXNM *a)
return false;
}

/* UNDEF accesses to D16-D31 if they don't exist */
if (dp && !dc_isar_feature(aa32_simd_r32, s) &&
((a->vm | a->vn | a->vd) & 0x10)) {
if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}

if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) {
/* UNDEF accesses to D16-D31 if they don't exist */
if (dp && !dc_isar_feature(aa32_simd_r32, s) &&
((a->vm | a->vn | a->vd) & 0x10)) {
return false;
}

Expand Down Expand Up @@ -419,13 +419,13 @@ static bool trans_VRINT(DisasContext *s, arg_VRINT *a)
return false;
}

/* UNDEF accesses to D16-D31 if they don't exist */
if (dp && !dc_isar_feature(aa32_simd_r32, s) &&
((a->vm | a->vd) & 0x10)) {
if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}

if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) {
/* UNDEF accesses to D16-D31 if they don't exist */
if (dp && !dc_isar_feature(aa32_simd_r32, s) &&
((a->vm | a->vd) & 0x10)) {
return false;
}

Expand Down Expand Up @@ -483,12 +483,12 @@ static bool trans_VCVT(DisasContext *s, arg_VCVT *a)
return false;
}

/* UNDEF accesses to D16-D31 if they don't exist */
if (dp && !dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) {
if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}

if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) {
/* UNDEF accesses to D16-D31 if they don't exist */
if (dp && !dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) {
return false;
}

Expand Down Expand Up @@ -1308,12 +1308,12 @@ static bool do_vfp_3op_dp(DisasContext *s, VFPGen3OpDPFn *fn,
TCGv_i64 f0, f1, fd;
TCGv_ptr fpst;

/* UNDEF accesses to D16-D31 if they don't exist */
if (!dc_isar_feature(aa32_simd_r32, s) && ((vd | vn | vm) & 0x10)) {
if (!dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}

if (!dc_isar_feature(aa32_fpdp_v2, s)) {
/* UNDEF accesses to D16-D31 if they don't exist */
if (!dc_isar_feature(aa32_simd_r32, s) && ((vd | vn | vm) & 0x10)) {
return false;
}

Expand Down Expand Up @@ -1457,12 +1457,12 @@ static bool do_vfp_2op_dp(DisasContext *s, VFPGen2OpDPFn *fn, int vd, int vm)
int veclen = s->vec_len;
TCGv_i64 f0, fd;

/* UNDEF accesses to D16-D31 if they don't exist */
if (!dc_isar_feature(aa32_simd_r32, s) && ((vd | vm) & 0x10)) {
if (!dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}

if (!dc_isar_feature(aa32_fpdp_v2, s)) {
/* UNDEF accesses to D16-D31 if they don't exist */
if (!dc_isar_feature(aa32_simd_r32, s) && ((vd | vm) & 0x10)) {
return false;
}

Expand Down Expand Up @@ -1827,7 +1827,9 @@ static bool trans_VFM_dp(DisasContext *s, arg_VFM_dp *a)
return false;
}

if (!dc_isar_feature(aa32_fpdp_v2, s)) {
/* UNDEF accesses to D16-D31 if they don't exist. */
if (!dc_isar_feature(aa32_simd_r32, s) &&
((a->vd | a->vn | a->vm) & 0x10)) {
return false;
}

Expand Down Expand Up @@ -1921,12 +1923,12 @@ static bool trans_VMOV_imm_dp(DisasContext *s, arg_VMOV_imm_dp *a)

vd = a->vd;

/* UNDEF accesses to D16-D31 if they don't exist. */
if (!dc_isar_feature(aa32_simd_r32, s) && (vd & 0x10)) {
if (!dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}

if (!dc_isar_feature(aa32_fpdp_v2, s)) {
/* UNDEF accesses to D16-D31 if they don't exist. */
if (!dc_isar_feature(aa32_simd_r32, s) && (vd & 0x10)) {
return false;
}

Expand Down Expand Up @@ -2060,6 +2062,10 @@ static bool trans_VCMP_dp(DisasContext *s, arg_VCMP_dp *a)
{
TCGv_i64 vd, vm;

if (!dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}

/* Vm/M bits must be zero for the Z variant */
if (a->z && a->vm != 0) {
return false;
Expand All @@ -2070,10 +2076,6 @@ static bool trans_VCMP_dp(DisasContext *s, arg_VCMP_dp *a)
return false;
}

if (!dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}

if (!vfp_access_check(s)) {
return true;
}
Expand Down Expand Up @@ -2134,16 +2136,16 @@ static bool trans_VCVT_f64_f16(DisasContext *s, arg_VCVT_f64_f16 *a)
TCGv_i32 tmp;
TCGv_i64 vd;

if (!dc_isar_feature(aa32_fp16_dpconv, s)) {
if (!dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}

/* UNDEF accesses to D16-D31 if they don't exist. */
if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) {
if (!dc_isar_feature(aa32_fp16_dpconv, s)) {
return false;
}

if (!dc_isar_feature(aa32_fpdp_v2, s)) {
/* UNDEF accesses to D16-D31 if they don't exist. */
if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) {
return false;
}

Expand Down Expand Up @@ -2200,16 +2202,16 @@ static bool trans_VCVT_f16_f64(DisasContext *s, arg_VCVT_f16_f64 *a)
TCGv_i32 tmp;
TCGv_i64 vm;

if (!dc_isar_feature(aa32_fp16_dpconv, s)) {
if (!dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}

/* UNDEF accesses to D16-D31 if they don't exist. */
if (!dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) {
if (!dc_isar_feature(aa32_fp16_dpconv, s)) {
return false;
}

if (!dc_isar_feature(aa32_fpdp_v2, s)) {
/* UNDEF accesses to D16-D31 if they don't exist. */
if (!dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) {
return false;
}

Expand Down Expand Up @@ -2260,16 +2262,16 @@ static bool trans_VRINTR_dp(DisasContext *s, arg_VRINTR_dp *a)
TCGv_ptr fpst;
TCGv_i64 tmp;

if (!dc_isar_feature(aa32_vrint, s)) {
if (!dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}

/* UNDEF accesses to D16-D31 if they don't exist. */
if (!dc_isar_feature(aa32_simd_r32, s) && ((a->vd | a->vm) & 0x10)) {
if (!dc_isar_feature(aa32_vrint, s)) {
return false;
}

if (!dc_isar_feature(aa32_fpdp_v2, s)) {
/* UNDEF accesses to D16-D31 if they don't exist. */
if (!dc_isar_feature(aa32_simd_r32, s) && ((a->vd | a->vm) & 0x10)) {
return false;
}

Expand Down Expand Up @@ -2321,16 +2323,16 @@ static bool trans_VRINTZ_dp(DisasContext *s, arg_VRINTZ_dp *a)
TCGv_i64 tmp;
TCGv_i32 tcg_rmode;

if (!dc_isar_feature(aa32_vrint, s)) {
if (!dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}

/* UNDEF accesses to D16-D31 if they don't exist. */
if (!dc_isar_feature(aa32_simd_r32, s) && ((a->vd | a->vm) & 0x10)) {
if (!dc_isar_feature(aa32_vrint, s)) {
return false;
}

if (!dc_isar_feature(aa32_fpdp_v2, s)) {
/* UNDEF accesses to D16-D31 if they don't exist. */
if (!dc_isar_feature(aa32_simd_r32, s) && ((a->vd | a->vm) & 0x10)) {
return false;
}

Expand Down Expand Up @@ -2380,16 +2382,16 @@ static bool trans_VRINTX_dp(DisasContext *s, arg_VRINTX_dp *a)
TCGv_ptr fpst;
TCGv_i64 tmp;

if (!dc_isar_feature(aa32_vrint, s)) {
if (!dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}

/* UNDEF accesses to D16-D31 if they don't exist. */
if (!dc_isar_feature(aa32_simd_r32, s) && ((a->vd | a->vm) & 0x10)) {
if (!dc_isar_feature(aa32_vrint, s)) {
return false;
}

if (!dc_isar_feature(aa32_fpdp_v2, s)) {
/* UNDEF accesses to D16-D31 if they don't exist. */
if (!dc_isar_feature(aa32_simd_r32, s) && ((a->vd | a->vm) & 0x10)) {
return false;
}

Expand All @@ -2412,12 +2414,12 @@ static bool trans_VCVT_sp(DisasContext *s, arg_VCVT_sp *a)
TCGv_i64 vd;
TCGv_i32 vm;

/* UNDEF accesses to D16-D31 if they don't exist. */
if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) {
if (!dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}

if (!dc_isar_feature(aa32_fpdp_v2, s)) {
/* UNDEF accesses to D16-D31 if they don't exist. */
if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) {
return false;
}

Expand All @@ -2440,12 +2442,12 @@ static bool trans_VCVT_dp(DisasContext *s, arg_VCVT_dp *a)
TCGv_i64 vm;
TCGv_i32 vd;

/* UNDEF accesses to D16-D31 if they don't exist. */
if (!dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) {
if (!dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}

if (!dc_isar_feature(aa32_fpdp_v2, s)) {
/* UNDEF accesses to D16-D31 if they don't exist. */
if (!dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) {
return false;
}

Expand Down Expand Up @@ -2494,12 +2496,12 @@ static bool trans_VCVT_int_dp(DisasContext *s, arg_VCVT_int_dp *a)
TCGv_i64 vd;
TCGv_ptr fpst;

/* UNDEF accesses to D16-D31 if they don't exist. */
if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) {
if (!dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}

if (!dc_isar_feature(aa32_fpdp_v2, s)) {
/* UNDEF accesses to D16-D31 if they don't exist. */
if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) {
return false;
}

Expand Down Expand Up @@ -2530,16 +2532,16 @@ static bool trans_VJCVT(DisasContext *s, arg_VJCVT *a)
TCGv_i32 vd;
TCGv_i64 vm;

if (!dc_isar_feature(aa32_jscvt, s)) {
if (!dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}

/* UNDEF accesses to D16-D31 if they don't exist. */
if (!dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) {
if (!dc_isar_feature(aa32_jscvt, s)) {
return false;
}

if (!dc_isar_feature(aa32_fpdp_v2, s)) {
/* UNDEF accesses to D16-D31 if they don't exist. */
if (!dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) {
return false;
}

Expand Down Expand Up @@ -2623,16 +2625,16 @@ static bool trans_VCVT_fix_dp(DisasContext *s, arg_VCVT_fix_dp *a)
TCGv_ptr fpst;
int frac_bits;

if (!arm_dc_feature(s, ARM_FEATURE_VFP3)) {
if (!dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}

/* UNDEF accesses to D16-D31 if they don't exist. */
if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) {
if (!arm_dc_feature(s, ARM_FEATURE_VFP3)) {
return false;
}

if (!dc_isar_feature(aa32_fpdp_v2, s)) {
/* UNDEF accesses to D16-D31 if they don't exist. */
if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) {
return false;
}

Expand Down Expand Up @@ -2723,12 +2725,12 @@ static bool trans_VCVT_dp_int(DisasContext *s, arg_VCVT_dp_int *a)
TCGv_i64 vm;
TCGv_ptr fpst;

/* UNDEF accesses to D16-D31 if they don't exist. */
if (!dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) {
if (!dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}

if (!dc_isar_feature(aa32_fpdp_v2, s)) {
/* UNDEF accesses to D16-D31 if they don't exist. */
if (!dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) {
return false;
}

Expand Down

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