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hw/intc: Move mtimer/mtimecmp to aclint
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Historically, The mtime/mtimecmp has been part of the CPU because
they are per hart entities. However, they actually belong to aclint
which is a MMIO device.

Move them to the ACLINT device. This also emulates the real hardware
more closely.

Reviewed-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Message-Id: <20220824221357.41070-2-atishp@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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@atishp04 @alistair23
atishp04 authored and alistair23 committed Sep 7, 2022
1 parent dc9acc9 commit 7cbcc53
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Showing 6 changed files with 47 additions and 30 deletions.
48 changes: 34 additions & 14 deletions hw/intc/riscv_aclint.c
View file
Expand Up @@ -32,6 +32,7 @@
#include "hw/intc/riscv_aclint.h"
#include "qemu/timer.h"
#include "hw/irq.h"
#include "migration/vmstate.h"

typedef struct riscv_aclint_mtimer_callback {
RISCVAclintMTimerState *s;
Expand Down Expand Up @@ -65,19 +66,22 @@ static void riscv_aclint_mtimer_write_timecmp(RISCVAclintMTimerState *mtimer,

uint64_t rtc_r = cpu_riscv_read_rtc(mtimer);

cpu->env.timecmp = value;
if (cpu->env.timecmp <= rtc_r) {
/* Compute the relative hartid w.r.t the socket */
hartid = hartid - mtimer->hartid_base;

mtimer->timecmp[hartid] = value;
if (mtimer->timecmp[hartid] <= rtc_r) {
/*
* If we're setting an MTIMECMP value in the "past",
* immediately raise the timer interrupt
*/
qemu_irq_raise(mtimer->timer_irqs[hartid - mtimer->hartid_base]);
qemu_irq_raise(mtimer->timer_irqs[hartid]);
return;
}

/* otherwise, set up the future timer interrupt */
qemu_irq_lower(mtimer->timer_irqs[hartid - mtimer->hartid_base]);
diff = cpu->env.timecmp - rtc_r;
qemu_irq_lower(mtimer->timer_irqs[hartid]);
diff = mtimer->timecmp[hartid] - rtc_r;
/* back to ns (note args switched in muldiv64) */
uint64_t ns_diff = muldiv64(diff, NANOSECONDS_PER_SECOND, timebase_freq);

Expand All @@ -102,7 +106,7 @@ static void riscv_aclint_mtimer_write_timecmp(RISCVAclintMTimerState *mtimer,
next = MIN(next, INT64_MAX);
}

timer_mod(cpu->env.timer, next);
timer_mod(mtimer->timers[hartid], next);
}

/*
Expand Down Expand Up @@ -133,11 +137,11 @@ static uint64_t riscv_aclint_mtimer_read(void *opaque, hwaddr addr,
"aclint-mtimer: invalid hartid: %zu", hartid);
} else if ((addr & 0x7) == 0) {
/* timecmp_lo for RV32/RV64 or timecmp for RV64 */
uint64_t timecmp = env->timecmp;
uint64_t timecmp = mtimer->timecmp[hartid];
return (size == 4) ? (timecmp & 0xFFFFFFFF) : timecmp;
} else if ((addr & 0x7) == 4) {
/* timecmp_hi */
uint64_t timecmp = env->timecmp;
uint64_t timecmp = mtimer->timecmp[hartid];
return (timecmp >> 32) & 0xFFFFFFFF;
} else {
qemu_log_mask(LOG_UNIMP,
Expand Down Expand Up @@ -177,7 +181,7 @@ static void riscv_aclint_mtimer_write(void *opaque, hwaddr addr,
} else if ((addr & 0x7) == 0) {
if (size == 4) {
/* timecmp_lo for RV32/RV64 */
uint64_t timecmp_hi = env->timecmp >> 32;
uint64_t timecmp_hi = mtimer->timecmp[hartid] >> 32;
riscv_aclint_mtimer_write_timecmp(mtimer, RISCV_CPU(cpu), hartid,
timecmp_hi << 32 | (value & 0xFFFFFFFF));
} else {
Expand All @@ -188,7 +192,7 @@ static void riscv_aclint_mtimer_write(void *opaque, hwaddr addr,
} else if ((addr & 0x7) == 4) {
if (size == 4) {
/* timecmp_hi for RV32/RV64 */
uint64_t timecmp_lo = env->timecmp;
uint64_t timecmp_lo = mtimer->timecmp[hartid];
riscv_aclint_mtimer_write_timecmp(mtimer, RISCV_CPU(cpu), hartid,
value << 32 | (timecmp_lo & 0xFFFFFFFF));
} else {
Expand Down Expand Up @@ -234,7 +238,7 @@ static void riscv_aclint_mtimer_write(void *opaque, hwaddr addr,
}
riscv_aclint_mtimer_write_timecmp(mtimer, RISCV_CPU(cpu),
mtimer->hartid_base + i,
env->timecmp);
mtimer->timecmp[i]);
}
return;
}
Expand Down Expand Up @@ -284,6 +288,8 @@ static void riscv_aclint_mtimer_realize(DeviceState *dev, Error **errp)
s->timer_irqs = g_new(qemu_irq, s->num_harts);
qdev_init_gpio_out(dev, s->timer_irqs, s->num_harts);

s->timers = g_new0(QEMUTimer *, s->num_harts);
s->timecmp = g_new0(uint64_t, s->num_harts);
/* Claim timer interrupt bits */
for (i = 0; i < s->num_harts; i++) {
RISCVCPU *cpu = RISCV_CPU(qemu_get_cpu(s->hartid_base + i));
Expand All @@ -310,13 +316,26 @@ static void riscv_aclint_mtimer_reset_enter(Object *obj, ResetType type)
riscv_aclint_mtimer_write(mtimer, mtimer->time_base, 0, 8);
}

static const VMStateDescription vmstate_riscv_mtimer = {
.name = "riscv_mtimer",
.version_id = 1,
.minimum_version_id = 1,
.fields = (VMStateField[]) {
VMSTATE_VARRAY_UINT32(timecmp, RISCVAclintMTimerState,
num_harts, 0,
vmstate_info_uint64, uint64_t),
VMSTATE_END_OF_LIST()
}
};

static void riscv_aclint_mtimer_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->realize = riscv_aclint_mtimer_realize;
device_class_set_props(dc, riscv_aclint_mtimer_properties);
ResettableClass *rc = RESETTABLE_CLASS(klass);
rc->phases.enter = riscv_aclint_mtimer_reset_enter;
dc->vmsd = &vmstate_riscv_mtimer;
}

static const TypeInfo riscv_aclint_mtimer_info = {
Expand All @@ -336,6 +355,7 @@ DeviceState *riscv_aclint_mtimer_create(hwaddr addr, hwaddr size,
{
int i;
DeviceState *dev = qdev_new(TYPE_RISCV_ACLINT_MTIMER);
RISCVAclintMTimerState *s = RISCV_ACLINT_MTIMER(dev);

assert(num_harts <= RISCV_ACLINT_MAX_HARTS);
assert(!(addr & 0x7));
Expand Down Expand Up @@ -366,11 +386,11 @@ DeviceState *riscv_aclint_mtimer_create(hwaddr addr, hwaddr size,
riscv_cpu_set_rdtime_fn(env, cpu_riscv_read_rtc, dev);
}

cb->s = RISCV_ACLINT_MTIMER(dev);
cb->s = s;
cb->num = i;
env->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
s->timers[i] = timer_new_ns(QEMU_CLOCK_VIRTUAL,
&riscv_aclint_mtimer_cb, cb);
env->timecmp = 0;
s->timecmp[i] = 0;

qdev_connect_gpio_out(dev, i,
qdev_get_gpio_in(DEVICE(rvcpu), IRQ_M_TIMER));
Expand Down
18 changes: 7 additions & 11 deletions hw/timer/ibex_timer.c
View file
Expand Up @@ -60,8 +60,6 @@ static uint64_t cpu_riscv_read_rtc(uint32_t timebase_freq)

static void ibex_timer_update_irqs(IbexTimerState *s)
{
CPUState *cs = qemu_get_cpu(0);
RISCVCPU *cpu = RISCV_CPU(cs);
uint64_t value = s->timer_compare_lower0 |
((uint64_t)s->timer_compare_upper0 << 32);
uint64_t next, diff;
Expand All @@ -73,9 +71,9 @@ static void ibex_timer_update_irqs(IbexTimerState *s)
}

/* Update the CPUs mtimecmp */
cpu->env.timecmp = value;
s->mtimecmp = value;

if (cpu->env.timecmp <= now) {
if (s->mtimecmp <= now) {
/*
* If the mtimecmp was in the past raise the interrupt now.
*/
Expand All @@ -91,17 +89,17 @@ static void ibex_timer_update_irqs(IbexTimerState *s)
qemu_irq_lower(s->m_timer_irq);
qemu_set_irq(s->irq, false);

diff = cpu->env.timecmp - now;
diff = s->mtimecmp - now;
next = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
muldiv64(diff,
NANOSECONDS_PER_SECOND,
s->timebase_freq);

if (next < qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)) {
/* We overflowed the timer, just set it as large as we can */
timer_mod(cpu->env.timer, 0x7FFFFFFFFFFFFFFF);
timer_mod(s->mtimer, 0x7FFFFFFFFFFFFFFF);
} else {
timer_mod(cpu->env.timer, next);
timer_mod(s->mtimer, next);
}
}

Expand All @@ -120,11 +118,9 @@ static void ibex_timer_reset(DeviceState *dev)
{
IbexTimerState *s = IBEX_TIMER(dev);

CPUState *cpu = qemu_get_cpu(0);
CPURISCVState *env = cpu->env_ptr;
env->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
s->mtimer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
&ibex_timer_cb, s);
env->timecmp = 0;
s->mtimecmp = 0;

s->timer_ctrl = 0x00000000;
s->timer_cfg0 = 0x00010000;
Expand Down
2 changes: 2 additions & 0 deletions include/hw/intc/riscv_aclint.h
View file
Expand Up @@ -32,6 +32,8 @@ typedef struct RISCVAclintMTimerState {
/*< private >*/
SysBusDevice parent_obj;
uint64_t time_delta;
uint64_t *timecmp;
QEMUTimer **timers;

/*< public >*/
MemoryRegion mmio;
Expand Down
2 changes: 2 additions & 0 deletions include/hw/timer/ibex_timer.h
View file
Expand Up @@ -33,6 +33,8 @@ OBJECT_DECLARE_SIMPLE_TYPE(IbexTimerState, IBEX_TIMER)
struct IbexTimerState {
/* <private> */
SysBusDevice parent_obj;
uint64_t mtimecmp;
QEMUTimer *mtimer; /* Internal timer for M-mode interrupt */

/* <public> */
MemoryRegion mmio;
Expand Down
2 changes: 0 additions & 2 deletions target/riscv/cpu.h
View file
Expand Up @@ -307,7 +307,6 @@ struct CPUArchState {
/* temporary htif regs */
uint64_t mfromhost;
uint64_t mtohost;
uint64_t timecmp;

/* physical memory protection */
pmp_table_t pmp_state;
Expand Down Expand Up @@ -362,7 +361,6 @@ struct CPUArchState {
float_status fp_status;

/* Fields from here on are preserved across CPU reset. */
QEMUTimer *timer; /* Internal timer */

hwaddr kernel_addr;
hwaddr fdt_addr;
Expand Down
5 changes: 2 additions & 3 deletions target/riscv/machine.c
View file
Expand Up @@ -307,8 +307,8 @@ static const VMStateDescription vmstate_pmu_ctr_state = {

const VMStateDescription vmstate_riscv_cpu = {
.name = "cpu",
.version_id = 3,
.minimum_version_id = 3,
.version_id = 4,
.minimum_version_id = 4,
.post_load = riscv_cpu_post_load,
.fields = (VMStateField[]) {
VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32),
Expand Down Expand Up @@ -359,7 +359,6 @@ const VMStateDescription vmstate_riscv_cpu = {
VMSTATE_UINTTL(env.mscratch, RISCVCPU),
VMSTATE_UINT64(env.mfromhost, RISCVCPU),
VMSTATE_UINT64(env.mtohost, RISCVCPU),
VMSTATE_UINT64(env.timecmp, RISCVCPU),

VMSTATE_END_OF_LIST()
},
Expand Down

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