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Merge tag 'pull-riscv-to-apply-20231107' of https://github.com/alista…
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…ir23/qemu into staging

Third RISC-V PR for 8.2

 * Rename ext_icboz to ext_zicboz
 * Rename ext_icbom to ext_zicbom
 * Rename ext_icsr to ext_zicsr
 * Rename ext_ifencei to ext_zifencei
 * Add RISC-V Virtual IRQs and IRQ filtering support
 * Change default linux-user cpu to 'max'
 * Update 'virt' machine core limit
 * Add query-cpu-model-expansion API
 * Rename epmp to smepmp and expose the extension
 * Clear pmp/smepmp bits on reset
 * Ignore pmp writes when RW=01
 * Support zicntr/zihpm flags and disable support
 * Correct CSR_MSECCFG operations
 * Update mail address for Weiwei Li
 * Update RISC-V vector crypto to ratified v1.0.0
 * Clear the Ibex/OpenTitan SPI interrupts even if disabled
 * Set the OpenTitan priv to 1.12.0
 * Support discontinuous PMU counters

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# gpg: Signature made Tue 07 Nov 2023 10:28:49 HKT
# gpg:                using RSA key 6AE902B6A7CA877D6D659296AF7C95130C538013
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 6AE9 02B6 A7CA 877D 6D65  9296 AF7C 9513 0C53 8013

* tag 'pull-riscv-to-apply-20231107' of https://github.com/alistair23/qemu: (49 commits)
  docs/about/deprecated: Document RISC-V "pmu-num" deprecation
  target/riscv: Add "pmu-mask" property to replace "pmu-num"
  target/riscv: Use existing PMU counter mask in FDT generation
  target/riscv: Don't assume PMU counters are continuous
  target/riscv: Propagate error from PMU setup
  target/riscv: cpu: Set the OpenTitan priv to 1.12.0
  hw/ssi: ibex_spi_host: Clear the interrupt even if disabled
  disas/riscv: Replace TABs with space
  disas/riscv: Add support for vector crypto extensions
  disas/riscv: Add rv_codec_vror_vi for vror.vi
  disas/riscv: Add rv_fmt_vd_vs2_uimm format
  target/riscv: Move vector crypto extensions to riscv_cpu_extensions
  target/riscv: Expose Zvks[c|g] extnesion properties
  target/riscv: Add cfg properties for Zvks[c|g] extensions
  target/riscv: Expose Zvkn[c|g] extnesion properties
  target/riscv: Add cfg properties for Zvkn[c|g] extensions
  target/riscv: Expose Zvkb extension property
  target/riscv: Replace Zvbb checking by Zvkb
  target/riscv: Add cfg property for Zvkb extension
  target/riscv: Expose Zvkt extension property
  ...

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
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@stefanhaRH
stefanhaRH committed Nov 7, 2023
2 parents 7494926 + bc5e844 commit 8aba939
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Showing 29 changed files with 1,326 additions and 258 deletions.
2 changes: 1 addition & 1 deletion MAINTAINERS
View file
Original file line number Diff line number Diff line change
Expand Up @@ -323,7 +323,7 @@ RISC-V TCG CPUs
M: Palmer Dabbelt <palmer@dabbelt.com>
M: Alistair Francis <alistair.francis@wdc.com>
M: Bin Meng <bin.meng@windriver.com>
R: Weiwei Li <liweiwei@iscas.ac.cn>
R: Weiwei Li <liwei1518@gmail.com>
R: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
R: Liu Zhiwei <zhiwei_liu@linux.alibaba.com>
L: qemu-riscv@nongnu.org
Expand Down
157 changes: 153 additions & 4 deletions disas/riscv.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -862,6 +862,47 @@ typedef enum {
rv_op_fltq_q = 831,
rv_op_fleq_h = 832,
rv_op_fltq_h = 833,
rv_op_vaesdf_vv = 834,
rv_op_vaesdf_vs = 835,
rv_op_vaesdm_vv = 836,
rv_op_vaesdm_vs = 837,
rv_op_vaesef_vv = 838,
rv_op_vaesef_vs = 839,
rv_op_vaesem_vv = 840,
rv_op_vaesem_vs = 841,
rv_op_vaeskf1_vi = 842,
rv_op_vaeskf2_vi = 843,
rv_op_vaesz_vs = 844,
rv_op_vandn_vv = 845,
rv_op_vandn_vx = 846,
rv_op_vbrev_v = 847,
rv_op_vbrev8_v = 848,
rv_op_vclmul_vv = 849,
rv_op_vclmul_vx = 850,
rv_op_vclmulh_vv = 851,
rv_op_vclmulh_vx = 852,
rv_op_vclz_v = 853,
rv_op_vcpop_v = 854,
rv_op_vctz_v = 855,
rv_op_vghsh_vv = 856,
rv_op_vgmul_vv = 857,
rv_op_vrev8_v = 858,
rv_op_vrol_vv = 859,
rv_op_vrol_vx = 860,
rv_op_vror_vv = 861,
rv_op_vror_vx = 862,
rv_op_vror_vi = 863,
rv_op_vsha2ch_vv = 864,
rv_op_vsha2cl_vv = 865,
rv_op_vsha2ms_vv = 866,
rv_op_vsm3c_vi = 867,
rv_op_vsm3me_vv = 868,
rv_op_vsm4k_vi = 869,
rv_op_vsm4r_vv = 870,
rv_op_vsm4r_vs = 871,
rv_op_vwsll_vv = 872,
rv_op_vwsll_vx = 873,
rv_op_vwsll_vi = 874,
} rv_op;

/* register names */
Expand Down Expand Up @@ -2008,6 +2049,47 @@ const rv_opcode_data rvi_opcode_data[] = {
{ "fltq.q", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 },
{ "fleq.h", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 },
{ "fltq.h", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 },
{ "vaesdf.vv", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
{ "vaesdf.vs", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
{ "vaesdm.vv", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
{ "vaesdm.vs", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
{ "vaesef.vv", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
{ "vaesef.vs", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
{ "vaesem.vv", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
{ "vaesem.vs", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
{ "vaeskf1.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm, NULL, 0, 0, 0 },
{ "vaeskf2.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm, NULL, 0, 0, 0 },
{ "vaesz.vs", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
{ "vandn.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
{ "vandn.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
{ "vbrev.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
{ "vbrev8.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
{ "vclmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
{ "vclmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
{ "vclmulh.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
{ "vclmulh.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
{ "vclz.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
{ "vcpop.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
{ "vctz.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
{ "vghsh.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1, NULL, 0, 0, 0 },
{ "vgmul.vv", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
{ "vrev8.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
{ "vrol.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
{ "vrol.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
{ "vror.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
{ "vror.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
{ "vror.vi", rv_codec_vror_vi, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 },
{ "vsha2ch.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1, NULL, 0, 0, 0 },
{ "vsha2cl.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1, NULL, 0, 0, 0 },
{ "vsha2ms.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1, NULL, 0, 0, 0 },
{ "vsm3c.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm, NULL, 0, 0, 0 },
{ "vsm3me.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1, NULL, 0, 0, 0 },
{ "vsm4k.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm, NULL, 0, 0, 0 },
{ "vsm4r.vv", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
{ "vsm4r.vs", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 },
{ "vwsll.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 },
{ "vwsll.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 },
{ "vwsll.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 },
};

/* CSR names */
Expand Down Expand Up @@ -3054,12 +3136,12 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
}
break;
case 89:
switch (((inst >> 12) & 0b111)) {
switch (((inst >> 12) & 0b111)) {
case 0: op = rv_op_fmvp_d_x; break;
}
break;
case 91:
switch (((inst >> 12) & 0b111)) {
switch (((inst >> 12) & 0b111)) {
case 0: op = rv_op_fmvp_q_x; break;
}
break;
Expand Down Expand Up @@ -3176,6 +3258,7 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
case 0:
switch ((inst >> 26) & 0b111111) {
case 0: op = rv_op_vadd_vv; break;
case 1: op = rv_op_vandn_vv; break;
case 2: op = rv_op_vsub_vv; break;
case 4: op = rv_op_vminu_vv; break;
case 5: op = rv_op_vmin_vv; break;
Expand All @@ -3198,6 +3281,8 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
}
break;
case 19: op = rv_op_vmsbc_vvm; break;
case 20: op = rv_op_vror_vv; break;
case 21: op = rv_op_vrol_vv; break;
case 23:
if (((inst >> 20) & 0b111111) == 32)
op = rv_op_vmv_v_v;
Expand Down Expand Up @@ -3226,6 +3311,7 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
case 47: op = rv_op_vnclip_wv; break;
case 48: op = rv_op_vwredsumu_vs; break;
case 49: op = rv_op_vwredsum_vs; break;
case 53: op = rv_op_vwsll_vv; break;
}
break;
case 1:
Expand Down Expand Up @@ -3323,6 +3409,8 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
case 9: op = rv_op_vaadd_vv; break;
case 10: op = rv_op_vasubu_vv; break;
case 11: op = rv_op_vasub_vv; break;
case 12: op = rv_op_vclmul_vv; break;
case 13: op = rv_op_vclmulh_vv; break;
case 16:
switch ((inst >> 15) & 0b11111) {
case 0: if ((inst >> 25) & 1) op = rv_op_vmv_x_s; break;
Expand All @@ -3338,6 +3426,12 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
case 5: op = rv_op_vsext_vf4; break;
case 6: op = rv_op_vzext_vf2; break;
case 7: op = rv_op_vsext_vf2; break;
case 8: op = rv_op_vbrev8_v; break;
case 9: op = rv_op_vrev8_v; break;
case 10: op = rv_op_vbrev_v; break;
case 12: op = rv_op_vclz_v; break;
case 13: op = rv_op_vctz_v; break;
case 14: op = rv_op_vcpop_v; break;
}
break;
case 20:
Expand Down Expand Up @@ -3406,6 +3500,7 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
}
break;
case 17: op = rv_op_vmadc_vim; break;
case 20: case 21: op = rv_op_vror_vi; break;
case 23:
if (((inst >> 20) & 0b111111) == 32)
op = rv_op_vmv_v_i;
Expand Down Expand Up @@ -3437,11 +3532,13 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
case 45: op = rv_op_vnsra_wi; break;
case 46: op = rv_op_vnclipu_wi; break;
case 47: op = rv_op_vnclip_wi; break;
case 53: op = rv_op_vwsll_vi; break;
}
break;
case 4:
switch ((inst >> 26) & 0b111111) {
case 0: op = rv_op_vadd_vx; break;
case 1: op = rv_op_vandn_vx; break;
case 2: op = rv_op_vsub_vx; break;
case 3: op = rv_op_vrsub_vx; break;
case 4: op = rv_op_vminu_vx; break;
Expand All @@ -3466,6 +3563,8 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
}
break;
case 19: op = rv_op_vmsbc_vxm; break;
case 20: op = rv_op_vror_vx; break;
case 21: op = rv_op_vrol_vx; break;
case 23:
if (((inst >> 20) & 0b111111) == 32)
op = rv_op_vmv_v_x;
Expand Down Expand Up @@ -3494,6 +3593,7 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
case 45: op = rv_op_vnsra_wx; break;
case 46: op = rv_op_vnclipu_wx; break;
case 47: op = rv_op_vnclip_wx; break;
case 53: op = rv_op_vwsll_vx; break;
}
break;
case 5:
Expand Down Expand Up @@ -3554,6 +3654,8 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
case 9: op = rv_op_vaadd_vx; break;
case 10: op = rv_op_vasubu_vx; break;
case 11: op = rv_op_vasub_vx; break;
case 12: op = rv_op_vclmul_vx; break;
case 13: op = rv_op_vclmulh_vx; break;
case 14: op = rv_op_vslide1up_vx; break;
case 15: op = rv_op_vslide1down_vx; break;
case 16:
Expand Down Expand Up @@ -3686,6 +3788,41 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
case 7: op = rv_op_csrrci; break;
}
break;
case 29:
if (((inst >> 25) & 1) == 1 && ((inst >> 12) & 0b111) == 2) {
switch ((inst >> 26) & 0b111111) {
case 32: op = rv_op_vsm3me_vv; break;
case 33: op = rv_op_vsm4k_vi; break;
case 34: op = rv_op_vaeskf1_vi; break;
case 40:
switch ((inst >> 15) & 0b11111) {
case 0: op = rv_op_vaesdm_vv; break;
case 1: op = rv_op_vaesdf_vv; break;
case 2: op = rv_op_vaesem_vv; break;
case 3: op = rv_op_vaesef_vv; break;
case 16: op = rv_op_vsm4r_vv; break;
case 17: op = rv_op_vgmul_vv; break;
}
break;
case 41:
switch ((inst >> 15) & 0b11111) {
case 0: op = rv_op_vaesdm_vs; break;
case 1: op = rv_op_vaesdf_vs; break;
case 2: op = rv_op_vaesem_vs; break;
case 3: op = rv_op_vaesef_vs; break;
case 7: op = rv_op_vaesz_vs; break;
case 16: op = rv_op_vsm4r_vs; break;
}
break;
case 42: op = rv_op_vaeskf2_vi; break;
case 43: op = rv_op_vsm3c_vi; break;
case 44: op = rv_op_vghsh_vv; break;
case 45: op = rv_op_vsha2ms_vv; break;
case 46: op = rv_op_vsha2ch_vv; break;
case 47: op = rv_op_vsha2cl_vv; break;
}
}
break;
case 30:
switch (((inst >> 22) & 0b1111111000) |
((inst >> 12) & 0b0000000111)) {
Expand Down Expand Up @@ -4011,6 +4148,12 @@ static uint32_t operand_vzimm10(rv_inst inst)
return (inst << 34) >> 54;
}

static uint32_t operand_vzimm6(rv_inst inst)
{
return ((inst << 37) >> 63) << 5 |
((inst << 44) >> 59);
}

static uint32_t operand_bs(rv_inst inst)
{
return (inst << 32) >> 62;
Expand Down Expand Up @@ -4393,6 +4536,12 @@ static void decode_inst_operands(rv_decode *dec, rv_isa isa)
dec->imm = operand_vimm(inst);
dec->vm = operand_vm(inst);
break;
case rv_codec_vror_vi:
dec->rd = operand_rd(inst);
dec->rs2 = operand_rs2(inst);
dec->imm = operand_vzimm6(inst);
dec->vm = operand_vm(inst);
break;
case rv_codec_vsetvli:
dec->rd = operand_rd(inst);
dec->rs1 = operand_rs1(inst);
Expand Down Expand Up @@ -4430,7 +4579,7 @@ static void decode_inst_operands(rv_decode *dec, rv_isa isa)
break;
case rv_codec_zcmt_jt:
dec->imm = operand_tbl_index(inst);
break;
break;
case rv_codec_fli:
dec->rd = operand_rd(inst);
dec->imm = operand_rs1(inst);
Expand Down Expand Up @@ -4677,7 +4826,7 @@ static void format_inst(char *buf, size_t buflen, size_t tab, rv_decode *dec)
append(buf, tmp, buflen);
break;
case 'u':
snprintf(tmp, sizeof(tmp), "%u", ((uint32_t)dec->imm & 0b11111));
snprintf(tmp, sizeof(tmp), "%u", ((uint32_t)dec->imm & 0b111111));
append(buf, tmp, buflen);
break;
case 'j':
Expand Down
2 changes: 2 additions & 0 deletions disas/riscv.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -152,6 +152,7 @@ typedef enum {
rv_codec_v_i,
rv_codec_vsetvli,
rv_codec_vsetivli,
rv_codec_vror_vi,
rv_codec_zcb_ext,
rv_codec_zcb_mul,
rv_codec_zcb_lb,
Expand Down Expand Up @@ -274,6 +275,7 @@ enum {
#define rv_fmt_vd_vs2_fs1_vm "O\tD,F,4m"
#define rv_fmt_vd_vs2_imm_vl "O\tD,F,il"
#define rv_fmt_vd_vs2_imm_vm "O\tD,F,im"
#define rv_fmt_vd_vs2_uimm "O\tD,F,u"
#define rv_fmt_vd_vs2_uimm_vm "O\tD,F,um"
#define rv_fmt_vd_vs1_vs2_vm "O\tD,E,Fm"
#define rv_fmt_vd_rs1_vs2_vm "O\tD,1,Fm"
Expand Down
12 changes: 12 additions & 0 deletions docs/about/deprecated.rst
View file
Original file line number Diff line number Diff line change
Expand Up @@ -413,6 +413,18 @@ Specifying the iSCSI password in plain text on the command line using the
used instead, to refer to a ``--object secret...`` instance that provides
a password via a file, or encrypted.

CPU device properties
'''''''''''''''''''''

``pmu-num=n`` on RISC-V CPUs (since 8.2)
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

In order to support more flexible counter configurations this has been replaced
by a ``pmu-mask`` property. If set of counters is continuous then the mask can
be calculated with ``((2 ^ n) - 1) << 3``. The least significant three bits
must be left clear.


Backwards compatibility
-----------------------

Expand Down
2 changes: 1 addition & 1 deletion docs/system/riscv/virt.rst
View file
Original file line number Diff line number Diff line change
Expand Up @@ -12,7 +12,7 @@ Supported devices

The ``virt`` machine supports the following devices:

* Up to 8 generic RV32GC/RV64GC cores, with optional extensions
* Up to 512 generic RV32GC/RV64GC cores, with optional extensions
* Core Local Interruptor (CLINT)
* Platform-Level Interrupt Controller (PLIC)
* CFI parallel NOR flash memory
Expand Down
2 changes: 1 addition & 1 deletion hw/riscv/boot.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -414,7 +414,7 @@ void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts
reset_vec[4] = 0x0182b283; /* ld t0, 24(t0) */
}

if (!harts->harts[0].cfg.ext_icsr) {
if (!harts->harts[0].cfg.ext_zicsr) {
/*
* The Zicsr extension has been disabled, so let's ensure we don't
* run the CSR instruction. Let's fill the address with a non
Expand Down
6 changes: 3 additions & 3 deletions hw/riscv/virt.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -263,12 +263,12 @@ static void create_fdt_socket_cpus(RISCVVirtState *s, int socket,
qemu_fdt_setprop_string(ms->fdt, cpu_name, "riscv,isa", name);
g_free(name);

if (cpu_ptr->cfg.ext_icbom) {
if (cpu_ptr->cfg.ext_zicbom) {
qemu_fdt_setprop_cell(ms->fdt, cpu_name, "riscv,cbom-block-size",
cpu_ptr->cfg.cbom_blocksize);
}

if (cpu_ptr->cfg.ext_icboz) {
if (cpu_ptr->cfg.ext_zicboz) {
qemu_fdt_setprop_cell(ms->fdt, cpu_name, "riscv,cboz-block-size",
cpu_ptr->cfg.cboz_blocksize);
}
Expand Down Expand Up @@ -722,7 +722,7 @@ static void create_fdt_pmu(RISCVVirtState *s)
pmu_name = g_strdup_printf("/pmu");
qemu_fdt_add_subnode(ms->fdt, pmu_name);
qemu_fdt_setprop_string(ms->fdt, pmu_name, "compatible", "riscv,pmu");
riscv_pmu_generate_fdt_node(ms->fdt, hart.cfg.pmu_num, pmu_name);
riscv_pmu_generate_fdt_node(ms->fdt, hart.pmu_avail_ctrs, pmu_name);

g_free(pmu_name);
}
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