Skip to content

Commit

Permalink
target/sparc: Inline FNEG, FABS
Browse files Browse the repository at this point in the history 
These are simple bit manipulation insns.
Begin using i128 for float128.
Implement FMOVq with do_qq.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Message-Id: <20231103173841.33651-6-richard.henderson@linaro.org>
  • Loading branch information
@rth7680
rth7680 committed Feb 2, 2024
1 parent 1addfac commit a6bc141
Show file tree
Hide file tree
Showing 3 changed files with 30 additions and 72 deletions.
34 changes: 0 additions & 34 deletions target/sparc/fop_helper.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -114,23 +114,6 @@ void helper_fdmulq(CPUSPARCState *env, float64 src1, float64 src2)
&env->fp_status);
}

float32 helper_fnegs(float32 src)
{
return float32_chs(src);
}

#ifdef TARGET_SPARC64
float64 helper_fnegd(float64 src)
{
return float64_chs(src);
}

F_HELPER(neg, q)
{
QT0 = float128_chs(QT1);
}
#endif

/* Integer to float conversion. */
float32 helper_fitos(CPUSPARCState *env, int32_t src)
{
Expand Down Expand Up @@ -229,23 +212,6 @@ int64_t helper_fqtox(CPUSPARCState *env)
}
#endif

float32 helper_fabss(float32 src)
{
return float32_abs(src);
}

#ifdef TARGET_SPARC64
float64 helper_fabsd(float64 src)
{
return float64_abs(src);
}

void helper_fabsq(CPUSPARCState *env)
{
QT0 = float128_abs(QT1);
}
#endif

float32 helper_fsqrts(CPUSPARCState *env, float32 src)
{
return float32_sqrt(src, &env->fp_status);
Expand Down
6 changes: 0 additions & 6 deletions target/sparc/helper.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -37,7 +37,6 @@ DEF_HELPER_FLAGS_5(st_asi, TCG_CALL_NO_WG, void, env, tl, i64, int, i32)
#endif
DEF_HELPER_FLAGS_1(check_ieee_exceptions, TCG_CALL_NO_WG, tl, env)
DEF_HELPER_FLAGS_2(set_fsr, TCG_CALL_NO_RWG, void, env, tl)
DEF_HELPER_FLAGS_1(fabss, TCG_CALL_NO_RWG_SE, f32, f32)
DEF_HELPER_FLAGS_2(fsqrts, TCG_CALL_NO_RWG, f32, env, f32)
DEF_HELPER_FLAGS_2(fsqrtd, TCG_CALL_NO_RWG, f64, env, f64)
DEF_HELPER_FLAGS_3(fcmps, TCG_CALL_NO_WG, tl, env, f32, f32)
Expand All @@ -48,7 +47,6 @@ DEF_HELPER_FLAGS_1(fsqrtq, TCG_CALL_NO_RWG, void, env)
DEF_HELPER_FLAGS_1(fcmpq, TCG_CALL_NO_WG, tl, env)
DEF_HELPER_FLAGS_1(fcmpeq, TCG_CALL_NO_WG, tl, env)
#ifdef TARGET_SPARC64
DEF_HELPER_FLAGS_1(fabsd, TCG_CALL_NO_RWG_SE, f64, f64)
DEF_HELPER_FLAGS_3(fcmps_fcc1, TCG_CALL_NO_WG, tl, env, f32, f32)
DEF_HELPER_FLAGS_3(fcmps_fcc2, TCG_CALL_NO_WG, tl, env, f32, f32)
DEF_HELPER_FLAGS_3(fcmps_fcc3, TCG_CALL_NO_WG, tl, env, f32, f32)
Expand All @@ -61,7 +59,6 @@ DEF_HELPER_FLAGS_3(fcmpes_fcc3, TCG_CALL_NO_WG, tl, env, f32, f32)
DEF_HELPER_FLAGS_3(fcmped_fcc1, TCG_CALL_NO_WG, tl, env, f64, f64)
DEF_HELPER_FLAGS_3(fcmped_fcc2, TCG_CALL_NO_WG, tl, env, f64, f64)
DEF_HELPER_FLAGS_3(fcmped_fcc3, TCG_CALL_NO_WG, tl, env, f64, f64)
DEF_HELPER_FLAGS_1(fabsq, TCG_CALL_NO_RWG, void, env)
DEF_HELPER_FLAGS_1(fcmpq_fcc1, TCG_CALL_NO_WG, tl, env)
DEF_HELPER_FLAGS_1(fcmpq_fcc2, TCG_CALL_NO_WG, tl, env)
DEF_HELPER_FLAGS_1(fcmpq_fcc3, TCG_CALL_NO_WG, tl, env)
Expand Down Expand Up @@ -90,15 +87,12 @@ DEF_HELPER_FLAGS_3(fdivs, TCG_CALL_NO_RWG, f32, env, f32, f32)
DEF_HELPER_FLAGS_3(fsmuld, TCG_CALL_NO_RWG, f64, env, f32, f32)
DEF_HELPER_FLAGS_3(fdmulq, TCG_CALL_NO_RWG, void, env, f64, f64)

DEF_HELPER_FLAGS_1(fnegs, TCG_CALL_NO_RWG_SE, f32, f32)
DEF_HELPER_FLAGS_2(fitod, TCG_CALL_NO_RWG_SE, f64, env, s32)
DEF_HELPER_FLAGS_2(fitoq, TCG_CALL_NO_RWG, void, env, s32)

DEF_HELPER_FLAGS_2(fitos, TCG_CALL_NO_RWG, f32, env, s32)

#ifdef TARGET_SPARC64
DEF_HELPER_FLAGS_1(fnegd, TCG_CALL_NO_RWG_SE, f64, f64)
DEF_HELPER_FLAGS_1(fnegq, TCG_CALL_NO_RWG, void, env)
DEF_HELPER_FLAGS_2(fxtos, TCG_CALL_NO_RWG, f32, env, s64)
DEF_HELPER_FLAGS_2(fxtod, TCG_CALL_NO_RWG, f64, env, s64)
DEF_HELPER_FLAGS_2(fxtoq, TCG_CALL_NO_RWG, void, env, s64)
Expand Down
62 changes: 30 additions & 32 deletions target/sparc/translate.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -43,9 +43,7 @@
#else
# define gen_helper_clear_softint(E, S) qemu_build_not_reached()
# define gen_helper_done(E) qemu_build_not_reached()
# define gen_helper_fabsd(D, S) qemu_build_not_reached()
# define gen_helper_flushw(E) qemu_build_not_reached()
# define gen_helper_fnegd(D, S) qemu_build_not_reached()
# define gen_helper_rdccr(D, E) qemu_build_not_reached()
# define gen_helper_rdcwp(D, E) qemu_build_not_reached()
# define gen_helper_restored(E) qemu_build_not_reached()
Expand All @@ -61,7 +59,6 @@
# define gen_helper_write_softint(E, S) qemu_build_not_reached()
# define gen_helper_wrpil(E, S) qemu_build_not_reached()
# define gen_helper_wrpstate(E, S) qemu_build_not_reached()
# define gen_helper_fabsq ({ qemu_build_not_reached(); NULL; })
# define gen_helper_fcmpeq16 ({ qemu_build_not_reached(); NULL; })
# define gen_helper_fcmpeq32 ({ qemu_build_not_reached(); NULL; })
# define gen_helper_fcmpgt16 ({ qemu_build_not_reached(); NULL; })
Expand All @@ -79,7 +76,6 @@
# define gen_helper_fmul8x16 ({ qemu_build_not_reached(); NULL; })
# define gen_helper_fmuld8sux16 ({ qemu_build_not_reached(); NULL; })
# define gen_helper_fmuld8ulx16 ({ qemu_build_not_reached(); NULL; })
# define gen_helper_fnegq ({ qemu_build_not_reached(); NULL; })
# define gen_helper_fpmerge ({ qemu_build_not_reached(); NULL; })
# define gen_helper_fqtox ({ qemu_build_not_reached(); NULL; })
# define gen_helper_fstox ({ qemu_build_not_reached(); NULL; })
Expand Down Expand Up @@ -1239,13 +1235,13 @@ static void gen_op_fmovs(TCGv_i32 dst, TCGv_i32 src)
static void gen_op_fnegs(TCGv_i32 dst, TCGv_i32 src)
{
gen_op_clear_ieee_excp_and_FTT();
gen_helper_fnegs(dst, src);
tcg_gen_xori_i32(dst, src, 1u << 31);
}

static void gen_op_fabss(TCGv_i32 dst, TCGv_i32 src)
{
gen_op_clear_ieee_excp_and_FTT();
gen_helper_fabss(dst, src);
tcg_gen_andi_i32(dst, src, ~(1u << 31));
}

static void gen_op_fmovd(TCGv_i64 dst, TCGv_i64 src)
Expand All @@ -1257,13 +1253,33 @@ static void gen_op_fmovd(TCGv_i64 dst, TCGv_i64 src)
static void gen_op_fnegd(TCGv_i64 dst, TCGv_i64 src)
{
gen_op_clear_ieee_excp_and_FTT();
gen_helper_fnegd(dst, src);
tcg_gen_xori_i64(dst, src, 1ull << 63);
}

static void gen_op_fabsd(TCGv_i64 dst, TCGv_i64 src)
{
gen_op_clear_ieee_excp_and_FTT();
gen_helper_fabsd(dst, src);
tcg_gen_andi_i64(dst, src, ~(1ull << 63));
}

static void gen_op_fnegq(TCGv_i128 dst, TCGv_i128 src)
{
TCGv_i64 l = tcg_temp_new_i64();
TCGv_i64 h = tcg_temp_new_i64();

tcg_gen_extr_i128_i64(l, h, src);
tcg_gen_xori_i64(h, h, 1ull << 63);
tcg_gen_concat_i64_i128(dst, l, h);
}

static void gen_op_fabsq(TCGv_i128 dst, TCGv_i128 src)
{
TCGv_i64 l = tcg_temp_new_i64();
TCGv_i64 h = tcg_temp_new_i64();

tcg_gen_extr_i128_i64(l, h, src);
tcg_gen_andi_i64(h, h, ~(1ull << 63));
tcg_gen_concat_i64_i128(dst, l, h);
}

#ifdef TARGET_SPARC64
Expand Down Expand Up @@ -4629,13 +4645,11 @@ TRANS(FiTOd, ALL, do_env_df, a, gen_helper_fitod)
TRANS(FsTOd, ALL, do_env_df, a, gen_helper_fstod)
TRANS(FsTOx, 64, do_env_df, a, gen_helper_fstox)

static bool trans_FMOVq(DisasContext *dc, arg_FMOVq *a)
static bool do_qq(DisasContext *dc, arg_r_r *a,
void (*func)(TCGv_i128, TCGv_i128))
{
TCGv_i128 t;

if (!avail_64(dc)) {
return false;
}
if (gen_trap_ifnofpu(dc)) {
return true;
}
Expand All @@ -4645,30 +4659,14 @@ static bool trans_FMOVq(DisasContext *dc, arg_FMOVq *a)

gen_op_clear_ieee_excp_and_FTT();
t = gen_load_fpr_Q(dc, a->rs);
func(t, t);
gen_store_fpr_Q(dc, a->rd, t);
return advance_pc(dc);
}

static bool do_qq(DisasContext *dc, arg_r_r *a,
void (*func)(TCGv_env))
{
if (gen_trap_ifnofpu(dc)) {
return true;
}
if (gen_trap_float128(dc)) {
return true;
}

gen_op_clear_ieee_excp_and_FTT();
gen_op_load_fpr_QT1(QFPREG(a->rs));
func(tcg_env);
gen_op_store_QT0_fpr(QFPREG(a->rd));
gen_update_fprs_dirty(dc, QFPREG(a->rd));
return advance_pc(dc);
}

TRANS(FNEGq, 64, do_qq, a, gen_helper_fnegq)
TRANS(FABSq, 64, do_qq, a, gen_helper_fabsq)
TRANS(FMOVq, 64, do_qq, a, tcg_gen_mov_i128)
TRANS(FNEGq, 64, do_qq, a, gen_op_fnegq)
TRANS(FABSq, 64, do_qq, a, gen_op_fabsq)

static bool do_env_qq(DisasContext *dc, arg_r_r *a,
void (*func)(TCGv_env))
Expand Down

0 comments on commit a6bc141

Please sign in to comment.