Skip to content

Commit

Permalink
target/sparc: Move TADD, TSUB, MULS to decodetree
Browse files Browse the repository at this point in the history 
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
  • Loading branch information
@rth7680
rth7680 committed Oct 25, 2023
1 parent c263685 commit a9aba13
Show file tree
Hide file tree
Showing 3 changed files with 29 additions and 30 deletions.
4 changes: 0 additions & 4 deletions target/sparc/helper.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -198,10 +198,8 @@ target_ulong helper_taddcctv(CPUSPARCState *env, target_ulong src1,
}

/* Only modify the CC after any exceptions have been generated. */
env->cc_op = CC_OP_TADDTV;
env->cc_src = src1;
env->cc_src2 = src2;
env->cc_dst = dst;
return dst;

tag_overflow:
Expand All @@ -226,10 +224,8 @@ target_ulong helper_tsubcctv(CPUSPARCState *env, target_ulong src1,
}

/* Only modify the CC after any exceptions have been generated. */
env->cc_op = CC_OP_TSUBTV;
env->cc_src = src1;
env->cc_src2 = src2;
env->cc_dst = dst;
return dst;

tag_overflow:
Expand Down
7 changes: 7 additions & 0 deletions target/sparc/insns.decode
View file
Original file line number Diff line number Diff line change
Expand Up @@ -32,6 +32,7 @@ CALL 01 i:s30
&r_r_ri_cc rd rs1 rs2_or_imm imm:bool cc:bool
@r_r_ri_cc .. rd:5 . cc:1 .... rs1:5 imm:1 rs2_or_imm:s13 &r_r_ri_cc
@r_r_ri_cc0 .. rd:5 ...... rs1:5 imm:1 rs2_or_imm:s13 &r_r_ri_cc cc=0
@r_r_ri_cc1 .. rd:5 ...... rs1:5 imm:1 rs2_or_imm:s13 &r_r_ri_cc cc=1

{
[
Expand Down Expand Up @@ -170,12 +171,18 @@ SUBC 10 ..... 0.1100 ..... . ............. @r_r_ri_cc
MULX 10 ..... 001001 ..... . ............. @r_r_ri_cc0
UMUL 10 ..... 0.1010 ..... . ............. @r_r_ri_cc
SMUL 10 ..... 0.1011 ..... . ............. @r_r_ri_cc
MULScc 10 ..... 100100 ..... . ............. @r_r_ri_cc1

UDIVX 10 ..... 001101 ..... . ............. @r_r_ri_cc0
SDIVX 10 ..... 101101 ..... . ............. @r_r_ri_cc0
UDIV 10 ..... 0.1110 ..... . ............. @r_r_ri_cc
SDIV 10 ..... 0.1111 ..... . ............. @r_r_ri_cc

TADDcc 10 ..... 100000 ..... . ............. @r_r_ri_cc1
TSUBcc 10 ..... 100001 ..... . ............. @r_r_ri_cc1
TADDccTV 10 ..... 100010 ..... . ............. @r_r_ri_cc1
TSUBccTV 10 ..... 100011 ..... . ............. @r_r_ri_cc1

Tcc_r 10 0 cond:4 111010 rs1:5 0 cc:1 0000000 rs2:5
{
# For v7, the entire simm13 field is present, but masked to 7 bits.
Expand Down
48 changes: 22 additions & 26 deletions target/sparc/translate.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -730,6 +730,16 @@ static void gen_op_sdivcc(TCGv dst, TCGv src1, TCGv src2)
gen_helper_sdiv_cc(dst, tcg_env, src1, src2);
}

static void gen_op_taddcctv(TCGv dst, TCGv src1, TCGv src2)
{
gen_helper_taddcctv(dst, tcg_env, src1, src2);
}

static void gen_op_tsubcctv(TCGv dst, TCGv src1, TCGv src2)
{
gen_helper_tsubcctv(dst, tcg_env, src1, src2);
}

// 1
static void gen_op_eval_ba(TCGv dst)
{
Expand Down Expand Up @@ -4146,6 +4156,11 @@ TRANS(ADD, ALL, do_arith, a, CC_OP_ADD,
TRANS(SUB, ALL, do_arith, a, CC_OP_SUB,
tcg_gen_sub_tl, tcg_gen_subi_tl, gen_op_sub_cc)

TRANS(TADDcc, ALL, do_arith, a, CC_OP_TADD, NULL, NULL, gen_op_add_cc)
TRANS(TSUBcc, ALL, do_arith, a, CC_OP_TSUB, NULL, NULL, gen_op_sub_cc)
TRANS(TADDccTV, ALL, do_arith, a, CC_OP_TADDTV, NULL, NULL, gen_op_taddcctv)
TRANS(TSUBccTV, ALL, do_arith, a, CC_OP_TSUBTV, NULL, NULL, gen_op_tsubcctv)

TRANS(AND, ALL, do_logic, a, tcg_gen_and_tl, tcg_gen_andi_tl)
TRANS(XOR, ALL, do_logic, a, tcg_gen_xor_tl, tcg_gen_xori_tl)
TRANS(ANDN, ALL, do_logic, a, tcg_gen_andc_tl, NULL)
Expand Down Expand Up @@ -4226,6 +4241,12 @@ static bool trans_SUBC(DisasContext *dc, arg_r_r_ri_cc *a)
}
}

static bool trans_MULScc(DisasContext *dc, arg_r_r_ri_cc *a)
{
update_psr(dc);
return do_arith(dc, a, CC_OP_ADD, NULL, NULL, gen_op_mulscc);
}

#define CHECK_IU_FEATURE(dc, FEATURE) \
if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \
goto illegal_insn;
Expand Down Expand Up @@ -4653,36 +4674,11 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn)
cpu_src2 = get_src2(dc, insn);
switch (xop) {
case 0x20: /* taddcc */
gen_op_add_cc(cpu_dst, cpu_src1, cpu_src2);
gen_store_gpr(dc, rd, cpu_dst);
tcg_gen_movi_i32(cpu_cc_op, CC_OP_TADD);
dc->cc_op = CC_OP_TADD;
break;
case 0x21: /* tsubcc */
gen_op_sub_cc(cpu_dst, cpu_src1, cpu_src2);
gen_store_gpr(dc, rd, cpu_dst);
tcg_gen_movi_i32(cpu_cc_op, CC_OP_TSUB);
dc->cc_op = CC_OP_TSUB;
break;
case 0x22: /* taddcctv */
gen_helper_taddcctv(cpu_dst, tcg_env,
cpu_src1, cpu_src2);
gen_store_gpr(dc, rd, cpu_dst);
dc->cc_op = CC_OP_TADDTV;
break;
case 0x23: /* tsubcctv */
gen_helper_tsubcctv(cpu_dst, tcg_env,
cpu_src1, cpu_src2);
gen_store_gpr(dc, rd, cpu_dst);
dc->cc_op = CC_OP_TSUBTV;
break;
case 0x24: /* mulscc */
update_psr(dc);
gen_op_mulscc(cpu_dst, cpu_src1, cpu_src2);
gen_store_gpr(dc, rd, cpu_dst);
tcg_gen_movi_i32(cpu_cc_op, CC_OP_ADD);
dc->cc_op = CC_OP_ADD;
break;
goto illegal_insn; /* in decodetree */
#ifndef TARGET_SPARC64
case 0x25: /* sll */
if (IS_IMM) { /* immediate */
Expand Down

0 comments on commit a9aba13

Please sign in to comment.