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target/i386: use TSTEQ/TSTNE to check flags
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The new conditions obviously come in handy when testing individual bits
of EFLAGS, and they make it possible to remove the .mask field of
CCPrepare.

Lowering to shift+and is done by the optimizer if necessary.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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@bonzini
bonzini committed Mar 5, 2024
1 parent 395d5d0 commit af87044
Showing 1 changed file with 16 additions and 16 deletions.
32 changes: 16 additions & 16 deletions target/i386/tcg/translate.c
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Original file line number Diff line number Diff line change
Expand Up @@ -995,8 +995,8 @@ static CCPrepare gen_prepare_eflags_c(DisasContext *s, TCGv reg)
case CC_OP_EFLAGS:
case CC_OP_SARB ... CC_OP_SARQ:
/* CC_SRC & 1 */
return (CCPrepare) { .cond = TCG_COND_NE,
.reg = cpu_cc_src, .mask = CC_C };
return (CCPrepare) { .cond = TCG_COND_TSTNE,
.reg = cpu_cc_src, .mask = -1, .imm = CC_C };

default:
/* The need to compute only C from CC_OP_DYNAMIC is important
Expand All @@ -1013,8 +1013,8 @@ static CCPrepare gen_prepare_eflags_c(DisasContext *s, TCGv reg)
static CCPrepare gen_prepare_eflags_p(DisasContext *s, TCGv reg)
{
gen_compute_eflags(s);
return (CCPrepare) { .cond = TCG_COND_NE, .reg = cpu_cc_src,
.mask = CC_P };
return (CCPrepare) { .cond = TCG_COND_TSTNE, .reg = cpu_cc_src,
.mask = -1, .imm = CC_P };
}

/* compute eflags.S to reg */
Expand All @@ -1028,8 +1028,8 @@ static CCPrepare gen_prepare_eflags_s(DisasContext *s, TCGv reg)
case CC_OP_ADCX:
case CC_OP_ADOX:
case CC_OP_ADCOX:
return (CCPrepare) { .cond = TCG_COND_NE, .reg = cpu_cc_src,
.mask = CC_S };
return (CCPrepare) { .cond = TCG_COND_TSTNE, .reg = cpu_cc_src,
.mask = -1, .imm = CC_S };
case CC_OP_CLR:
case CC_OP_POPCNT:
return (CCPrepare) { .cond = TCG_COND_NEVER, .mask = -1 };
Expand Down Expand Up @@ -1057,8 +1057,8 @@ static CCPrepare gen_prepare_eflags_o(DisasContext *s, TCGv reg)
.reg = cpu_cc_src, .mask = -1 };
default:
gen_compute_eflags(s);
return (CCPrepare) { .cond = TCG_COND_NE, .reg = cpu_cc_src,
.mask = CC_O };
return (CCPrepare) { .cond = TCG_COND_TSTNE, .reg = cpu_cc_src,
.mask = -1, .imm = CC_O };
}
}

Expand All @@ -1073,8 +1073,8 @@ static CCPrepare gen_prepare_eflags_z(DisasContext *s, TCGv reg)
case CC_OP_ADCX:
case CC_OP_ADOX:
case CC_OP_ADCOX:
return (CCPrepare) { .cond = TCG_COND_NE, .reg = cpu_cc_src,
.mask = CC_Z };
return (CCPrepare) { .cond = TCG_COND_TSTNE, .reg = cpu_cc_src,
.mask = -1, .imm = CC_Z };
case CC_OP_CLR:
return (CCPrepare) { .cond = TCG_COND_ALWAYS, .mask = -1 };
case CC_OP_POPCNT:
Expand Down Expand Up @@ -1152,8 +1152,8 @@ static CCPrepare gen_prepare_cc(DisasContext *s, int b, TCGv reg)
break;
case JCC_BE:
gen_compute_eflags(s);
cc = (CCPrepare) { .cond = TCG_COND_NE, .reg = cpu_cc_src,
.mask = CC_Z | CC_C };
cc = (CCPrepare) { .cond = TCG_COND_TSTNE, .reg = cpu_cc_src,
.mask = -1, .imm = CC_Z | CC_C };
break;
case JCC_S:
cc = gen_prepare_eflags_s(s, reg);
Expand All @@ -1167,8 +1167,8 @@ static CCPrepare gen_prepare_cc(DisasContext *s, int b, TCGv reg)
reg = s->tmp0;
}
tcg_gen_addi_tl(reg, cpu_cc_src, CC_O - CC_S);
cc = (CCPrepare) { .cond = TCG_COND_NE, .reg = reg,
.mask = CC_O };
cc = (CCPrepare) { .cond = TCG_COND_TSTNE, .reg = reg,
.mask = -1, .imm = CC_O };
break;
default:
case JCC_LE:
Expand All @@ -1177,8 +1177,8 @@ static CCPrepare gen_prepare_cc(DisasContext *s, int b, TCGv reg)
reg = s->tmp0;
}
tcg_gen_addi_tl(reg, cpu_cc_src, CC_O - CC_S);
cc = (CCPrepare) { .cond = TCG_COND_NE, .reg = reg,
.mask = CC_O | CC_Z };
cc = (CCPrepare) { .cond = TCG_COND_TSTNE, .reg = reg,
.mask = -1, .imm = CC_O | CC_Z };
break;
}
break;
Expand Down

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