target/mips/mips-defs: Introduce CPU_MIPS64 and cpu_type_is_64bit()

MIPS 64-bit ISA is introduced with MIPS3. Introduce the CPU_MIPS64 definition aliased to the MIPS3 ISA, and the cpu_type_is_64bit() method to check if a CPU supports this ISA (thus is 64-bit). Suggested-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210104221154.3127610-5-f4bug@amsat.org>
qemu · Jan 14, 2021 · b0586b3 · b0586b3
1 parent 8b0ea9b
commit b0586b3
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Showing 2 changed files with 8 additions and 1 deletion.
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
@@ -1305,6 +1305,11 @@ static inline bool ase_mt_available(CPUMIPSState *env)
     return env->CP0_Config3 & (1 << CP0C3_MT);
 }
 
+static inline bool cpu_type_is_64bit(const char *cpu_type)
+{
+    return cpu_type_supports_isa(cpu_type, CPU_MIPS64);
+}
+
 void cpu_set_exception_base(int vp_index, target_ulong address);
 
 /* addr.c */

diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h
@@ -13,7 +13,7 @@
  */
 #define ISA_MIPS1         0x0000000000000001ULL
 #define ISA_MIPS2         0x0000000000000002ULL
-#define ISA_MIPS3         0x0000000000000004ULL
+#define ISA_MIPS3         0x0000000000000004ULL /* 64-bit */
 #define ISA_MIPS4         0x0000000000000008ULL
 #define ISA_MIPS5         0x0000000000000010ULL
 #define ISA_MIPS32        0x0000000000000020ULL
@@ -71,6 +71,8 @@
 #define CPU_LOONGSON2E  (CPU_MIPS3 | INSN_LOONGSON2E)
 #define CPU_LOONGSON2F  (CPU_MIPS3 | INSN_LOONGSON2F | ASE_LMMI)
 
+#define CPU_MIPS64      (ISA_MIPS3)
+
 /* MIPS Technologies "Release 1" */
 #define CPU_MIPS32R1    (CPU_MIPS2 | ISA_MIPS32)
 #define CPU_MIPS64R1    (CPU_MIPS5 | CPU_MIPS32R1 | ISA_MIPS64)