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target/ppc: Implement xxgenpcv[bhwd]m instruction
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Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220225210936.1749575-36-matheus.ferst@eldorado.org.br>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
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@mferst @legoater
mferst authored and legoater committed Mar 2, 2022
1 parent 1015fca commit b090f4f
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Showing 4 changed files with 160 additions and 0 deletions.
16 changes: 16 additions & 0 deletions target/ppc/helper.h
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Expand Up @@ -494,6 +494,22 @@ DEF_HELPER_3(xvrspic, void, env, vsr, vsr)
DEF_HELPER_3(xvrspim, void, env, vsr, vsr)
DEF_HELPER_3(xvrspip, void, env, vsr, vsr)
DEF_HELPER_3(xvrspiz, void, env, vsr, vsr)
DEF_HELPER_FLAGS_2(XXGENPCVBM_be_exp, TCG_CALL_NO_RWG, void, vsr, avr)
DEF_HELPER_FLAGS_2(XXGENPCVBM_be_comp, TCG_CALL_NO_RWG, void, vsr, avr)
DEF_HELPER_FLAGS_2(XXGENPCVBM_le_exp, TCG_CALL_NO_RWG, void, vsr, avr)
DEF_HELPER_FLAGS_2(XXGENPCVBM_le_comp, TCG_CALL_NO_RWG, void, vsr, avr)
DEF_HELPER_FLAGS_2(XXGENPCVHM_be_exp, TCG_CALL_NO_RWG, void, vsr, avr)
DEF_HELPER_FLAGS_2(XXGENPCVHM_be_comp, TCG_CALL_NO_RWG, void, vsr, avr)
DEF_HELPER_FLAGS_2(XXGENPCVHM_le_exp, TCG_CALL_NO_RWG, void, vsr, avr)
DEF_HELPER_FLAGS_2(XXGENPCVHM_le_comp, TCG_CALL_NO_RWG, void, vsr, avr)
DEF_HELPER_FLAGS_2(XXGENPCVWM_be_exp, TCG_CALL_NO_RWG, void, vsr, avr)
DEF_HELPER_FLAGS_2(XXGENPCVWM_be_comp, TCG_CALL_NO_RWG, void, vsr, avr)
DEF_HELPER_FLAGS_2(XXGENPCVWM_le_exp, TCG_CALL_NO_RWG, void, vsr, avr)
DEF_HELPER_FLAGS_2(XXGENPCVWM_le_comp, TCG_CALL_NO_RWG, void, vsr, avr)
DEF_HELPER_FLAGS_2(XXGENPCVDM_be_exp, TCG_CALL_NO_RWG, void, vsr, avr)
DEF_HELPER_FLAGS_2(XXGENPCVDM_be_comp, TCG_CALL_NO_RWG, void, vsr, avr)
DEF_HELPER_FLAGS_2(XXGENPCVDM_le_exp, TCG_CALL_NO_RWG, void, vsr, avr)
DEF_HELPER_FLAGS_2(XXGENPCVDM_le_comp, TCG_CALL_NO_RWG, void, vsr, avr)
DEF_HELPER_4(xxextractuw, void, env, vsr, vsr, i32)
DEF_HELPER_FLAGS_5(XXPERMX, TCG_CALL_NO_RWG, void, vsr, vsr, vsr, vsr, tl)
DEF_HELPER_4(xxinsertw, void, env, vsr, vsr, i32)
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10 changes: 10 additions & 0 deletions target/ppc/insn32.decode
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Expand Up @@ -119,6 +119,9 @@
@X_bfl ...... bf:3 - l:1 ra:5 rb:5 ..........- &X_bfl

%x_xt 0:1 21:5
&X_imm5 xt imm:uint8_t vrb
@X_imm5 ...... ..... imm:5 vrb:5 .......... . &X_imm5 xt=%x_xt

&X_imm8 xt imm:uint8_t
@X_imm8 ...... ..... .. imm:8 .......... . &X_imm8 xt=%x_xt

Expand Down Expand Up @@ -615,6 +618,13 @@ XXPERMDI 111100 ..... ..... ..... 0 .. 01010 ... @XX3_dm

XXSEL 111100 ..... ..... ..... ..... 11 .... @XX4

## VSX Vector Generate PCV

XXGENPCVBM 111100 ..... ..... ..... 1110010100 . @X_imm5
XXGENPCVHM 111100 ..... ..... ..... 1110010101 . @X_imm5
XXGENPCVWM 111100 ..... ..... ..... 1110110100 . @X_imm5
XXGENPCVDM 111100 ..... ..... ..... 1110110101 . @X_imm5

## VSX Vector Load Special Value Instruction

LXVKQ 111100 ..... 11111 ..... 0101101000 . @X_uim5
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91 changes: 91 additions & 0 deletions target/ppc/int_helper.c
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Expand Up @@ -1072,6 +1072,97 @@ void helper_VPERMR(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c)
*r = result;
}

#define XXGENPCV(NAME, SZ) \
void glue(helper_, glue(NAME, _be_exp))(ppc_vsr_t *t, ppc_vsr_t *b) \
{ \
ppc_vsr_t tmp; \
\
/* Initialize tmp with the result of an all-zeros mask */ \
tmp.VsrD(0) = 0x1011121314151617; \
tmp.VsrD(1) = 0x18191A1B1C1D1E1F; \
\
/* Iterate over the most significant byte of each element */ \
for (int i = 0, j = 0; i < ARRAY_SIZE(b->u8); i += SZ) { \
if (b->VsrB(i) & 0x80) { \
/* Update each byte of the element */ \
for (int k = 0; k < SZ; k++) { \
tmp.VsrB(i + k) = j + k; \
} \
j += SZ; \
} \
} \
\
*t = tmp; \
} \
\
void glue(helper_, glue(NAME, _be_comp))(ppc_vsr_t *t, ppc_vsr_t *b)\
{ \
ppc_vsr_t tmp = { .u64 = { 0, 0 } }; \
\
/* Iterate over the most significant byte of each element */ \
for (int i = 0, j = 0; i < ARRAY_SIZE(b->u8); i += SZ) { \
if (b->VsrB(i) & 0x80) { \
/* Update each byte of the element */ \
for (int k = 0; k < SZ; k++) { \
tmp.VsrB(j + k) = i + k; \
} \
j += SZ; \
} \
} \
\
*t = tmp; \
} \
\
void glue(helper_, glue(NAME, _le_exp))(ppc_vsr_t *t, ppc_vsr_t *b) \
{ \
ppc_vsr_t tmp; \
\
/* Initialize tmp with the result of an all-zeros mask */ \
tmp.VsrD(0) = 0x1F1E1D1C1B1A1918; \
tmp.VsrD(1) = 0x1716151413121110; \
\
/* Iterate over the most significant byte of each element */ \
for (int i = 0, j = 0; i < ARRAY_SIZE(b->u8); i += SZ) { \
/* Reverse indexing of "i" */ \
const int idx = ARRAY_SIZE(b->u8) - i - SZ; \
if (b->VsrB(idx) & 0x80) { \
/* Update each byte of the element */ \
for (int k = 0, rk = SZ - 1; k < SZ; k++, rk--) { \
tmp.VsrB(idx + rk) = j + k; \
} \
j += SZ; \
} \
} \
\
*t = tmp; \
} \
\
void glue(helper_, glue(NAME, _le_comp))(ppc_vsr_t *t, ppc_vsr_t *b)\
{ \
ppc_vsr_t tmp = { .u64 = { 0, 0 } }; \
\
/* Iterate over the most significant byte of each element */ \
for (int i = 0, j = 0; i < ARRAY_SIZE(b->u8); i += SZ) { \
if (b->VsrB(ARRAY_SIZE(b->u8) - i - SZ) & 0x80) { \
/* Update each byte of the element */ \
for (int k = 0, rk = SZ - 1; k < SZ; k++, rk--) { \
/* Reverse indexing of "j" */ \
const int idx = ARRAY_SIZE(b->u8) - j - SZ; \
tmp.VsrB(idx + rk) = i + k; \
} \
j += SZ; \
} \
} \
\
*t = tmp; \
}

XXGENPCV(XXGENPCVBM, 1)
XXGENPCV(XXGENPCVHM, 2)
XXGENPCV(XXGENPCVWM, 4)
XXGENPCV(XXGENPCVDM, 8)
#undef XXGENPCV

#if defined(HOST_WORDS_BIGENDIAN)
#define VBPERMQ_INDEX(avr, i) ((avr)->u8[(i)])
#define VBPERMD_INDEX(i) (i)
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43 changes: 43 additions & 0 deletions target/ppc/translate/vsx-impl.c.inc
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Expand Up @@ -1256,6 +1256,49 @@ static bool trans_XXPERMX(DisasContext *ctx, arg_8RR_XX4_uim3 *a)
return true;
}

#define XXGENPCV(NAME) \
static bool trans_##NAME(DisasContext *ctx, arg_X_imm5 *a) \
{ \
TCGv_ptr xt, vrb; \
\
REQUIRE_INSNS_FLAGS2(ctx, ISA310); \
REQUIRE_VSX(ctx); \
\
if (a->imm & ~0x3) { \
gen_invalid(ctx); \
return true; \
} \
\
xt = gen_vsr_ptr(a->xt); \
vrb = gen_avr_ptr(a->vrb); \
\
switch (a->imm) { \
case 0b00000: /* Big-Endian expansion */ \
glue(gen_helper_, glue(NAME, _be_exp))(xt, vrb); \
break; \
case 0b00001: /* Big-Endian compression */ \
glue(gen_helper_, glue(NAME, _be_comp))(xt, vrb); \
break; \
case 0b00010: /* Little-Endian expansion */ \
glue(gen_helper_, glue(NAME, _le_exp))(xt, vrb); \
break; \
case 0b00011: /* Little-Endian compression */ \
glue(gen_helper_, glue(NAME, _le_comp))(xt, vrb); \
break; \
} \
\
tcg_temp_free_ptr(xt); \
tcg_temp_free_ptr(vrb); \
\
return true; \
}

XXGENPCV(XXGENPCVBM)
XXGENPCV(XXGENPCVHM)
XXGENPCV(XXGENPCVWM)
XXGENPCV(XXGENPCVDM)
#undef XXGENPCV

#define GEN_VSX_HELPER_VSX_MADD(name, op1, aop, mop, inval, type) \
static void gen_##name(DisasContext *ctx) \
{ \
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