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Merge tag 'pull-aspeed-20240227' of https://github.com/legoater/qemu …
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…into staging

aspeed queue:

* Add support for UART0, in preparation of AST2700 models

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* tag 'pull-aspeed-20240227' of https://github.com/legoater/qemu:
  aspeed: fix hardcode boot address 0
  aspeed: introduce a new UART0 device name

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@pm215
pm215 committed Feb 27, 2024
2 parents dccbaf0 + db052d0 commit b48ff1b
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Showing 6 changed files with 39 additions and 13 deletions.
17 changes: 11 additions & 6 deletions hw/arm/aspeed.c
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Original file line number Diff line number Diff line change
Expand Up @@ -289,12 +289,14 @@ static void aspeed_install_boot_rom(AspeedMachineState *bmc, BlockBackend *blk,
uint64_t rom_size)
{
AspeedSoCState *soc = bmc->soc;
AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(soc);

memory_region_init_rom(&bmc->boot_rom, NULL, "aspeed.boot_rom", rom_size,
&error_abort);
memory_region_add_subregion_overlap(&soc->spi_boot_container, 0,
&bmc->boot_rom, 1);
write_boot_rom(blk, ASPEED_SOC_SPI_BOOT_ADDR, rom_size, &error_abort);
write_boot_rom(blk, sc->memmap[ASPEED_DEV_SPI_BOOT],
rom_size, &error_abort);
}

void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype,
Expand Down Expand Up @@ -342,7 +344,7 @@ static void connect_serial_hds_to_uarts(AspeedMachineState *bmc)
int uart_chosen = bmc->uart_chosen ? bmc->uart_chosen : amc->uart_default;

aspeed_soc_uart_set_chr(s, uart_chosen, serial_hd(0));
for (int i = 1, uart = ASPEED_DEV_UART1; i < sc->uarts_num; i++, uart++) {
for (int i = 1, uart = sc->uarts_base; i < sc->uarts_num; i++, uart++) {
if (uart == uart_chosen) {
continue;
}
Expand Down Expand Up @@ -1094,7 +1096,7 @@ static char *aspeed_get_bmc_console(Object *obj, Error **errp)
AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(bmc);
int uart_chosen = bmc->uart_chosen ? bmc->uart_chosen : amc->uart_default;

return g_strdup_printf("uart%d", uart_chosen - ASPEED_DEV_UART1 + 1);
return g_strdup_printf("uart%d", aspeed_uart_index(uart_chosen));
}

static void aspeed_set_bmc_console(Object *obj, const char *value, Error **errp)
Expand All @@ -1103,18 +1105,21 @@ static void aspeed_set_bmc_console(Object *obj, const char *value, Error **errp)
AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(bmc);
AspeedSoCClass *sc = ASPEED_SOC_CLASS(object_class_by_name(amc->soc_name));
int val;
int uart_first = aspeed_uart_first(sc);
int uart_last = aspeed_uart_last(sc);

if (sscanf(value, "uart%u", &val) != 1) {
error_setg(errp, "Bad value for \"uart\" property");
return;
}

/* The number of UART depends on the SoC */
if (val < 1 || val > sc->uarts_num) {
error_setg(errp, "\"uart\" should be in range [1 - %d]", sc->uarts_num);
if (val < uart_first || val > uart_last) {
error_setg(errp, "\"uart\" should be in range [%d - %d]",
uart_first, uart_last);
return;
}
bmc->uart_chosen = ASPEED_DEV_UART1 + val - 1;
bmc->uart_chosen = val + ASPEED_DEV_UART0;
}

static void aspeed_machine_class_props_init(ObjectClass *oc)
Expand Down
1 change: 1 addition & 0 deletions hw/arm/aspeed_ast10x0.c
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Original file line number Diff line number Diff line change
Expand Up @@ -436,6 +436,7 @@ static void aspeed_soc_ast1030_class_init(ObjectClass *klass, void *data)
sc->wdts_num = 4;
sc->macs_num = 1;
sc->uarts_num = 13;
sc->uarts_base = ASPEED_DEV_UART1;
sc->irqmap = aspeed_soc_ast1030_irqmap;
sc->memmap = aspeed_soc_ast1030_memmap;
sc->num_cpus = 1;
Expand Down
6 changes: 4 additions & 2 deletions hw/arm/aspeed_ast2400.c
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Original file line number Diff line number Diff line change
Expand Up @@ -26,7 +26,7 @@
#define ASPEED_SOC_IOMEM_SIZE 0x00200000

static const hwaddr aspeed_soc_ast2400_memmap[] = {
[ASPEED_DEV_SPI_BOOT] = ASPEED_SOC_SPI_BOOT_ADDR,
[ASPEED_DEV_SPI_BOOT] = 0x00000000,
[ASPEED_DEV_IOMEM] = 0x1E600000,
[ASPEED_DEV_FMC] = 0x1E620000,
[ASPEED_DEV_SPI1] = 0x1E630000,
Expand Down Expand Up @@ -61,7 +61,7 @@ static const hwaddr aspeed_soc_ast2400_memmap[] = {
};

static const hwaddr aspeed_soc_ast2500_memmap[] = {
[ASPEED_DEV_SPI_BOOT] = ASPEED_SOC_SPI_BOOT_ADDR,
[ASPEED_DEV_SPI_BOOT] = 0x00000000,
[ASPEED_DEV_IOMEM] = 0x1E600000,
[ASPEED_DEV_FMC] = 0x1E620000,
[ASPEED_DEV_SPI1] = 0x1E630000,
Expand Down Expand Up @@ -523,6 +523,7 @@ static void aspeed_soc_ast2400_class_init(ObjectClass *oc, void *data)
sc->wdts_num = 2;
sc->macs_num = 2;
sc->uarts_num = 5;
sc->uarts_base = ASPEED_DEV_UART1;
sc->irqmap = aspeed_soc_ast2400_irqmap;
sc->memmap = aspeed_soc_ast2400_memmap;
sc->num_cpus = 1;
Expand Down Expand Up @@ -551,6 +552,7 @@ static void aspeed_soc_ast2500_class_init(ObjectClass *oc, void *data)
sc->wdts_num = 3;
sc->macs_num = 2;
sc->uarts_num = 5;
sc->uarts_base = ASPEED_DEV_UART1;
sc->irqmap = aspeed_soc_ast2500_irqmap;
sc->memmap = aspeed_soc_ast2500_memmap;
sc->num_cpus = 1;
Expand Down
3 changes: 2 additions & 1 deletion hw/arm/aspeed_ast2600.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -22,7 +22,7 @@
#define ASPEED_SOC_DPMCU_SIZE 0x00040000

static const hwaddr aspeed_soc_ast2600_memmap[] = {
[ASPEED_DEV_SPI_BOOT] = ASPEED_SOC_SPI_BOOT_ADDR,
[ASPEED_DEV_SPI_BOOT] = 0x00000000,
[ASPEED_DEV_SRAM] = 0x10000000,
[ASPEED_DEV_DPMCU] = 0x18000000,
/* 0x16000000 0x17FFFFFF : AHB BUS do LPC Bus bridge */
Expand Down Expand Up @@ -666,6 +666,7 @@ static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data)
sc->wdts_num = 4;
sc->macs_num = 4;
sc->uarts_num = 13;
sc->uarts_base = ASPEED_DEV_UART1;
sc->irqmap = aspeed_soc_ast2600_irqmap;
sc->memmap = aspeed_soc_ast2600_memmap;
sc->num_cpus = 2;
Expand Down
6 changes: 4 additions & 2 deletions hw/arm/aspeed_soc_common.c
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Original file line number Diff line number Diff line change
Expand Up @@ -36,7 +36,7 @@ bool aspeed_soc_uart_realize(AspeedSoCState *s, Error **errp)
AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
SerialMM *smm;

for (int i = 0, uart = ASPEED_DEV_UART1; i < sc->uarts_num; i++, uart++) {
for (int i = 0, uart = sc->uarts_base; i < sc->uarts_num; i++, uart++) {
smm = &s->uart[i];

/* Chardev property is set by the machine. */
Expand All @@ -58,7 +58,9 @@ bool aspeed_soc_uart_realize(AspeedSoCState *s, Error **errp)
void aspeed_soc_uart_set_chr(AspeedSoCState *s, int dev, Chardev *chr)
{
AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
int i = dev - ASPEED_DEV_UART1;
int uart_first = aspeed_uart_first(sc);
int uart_index = aspeed_uart_index(dev);
int i = uart_index - uart_first;

g_assert(0 <= i && i < ARRAY_SIZE(s->uart) && i < sc->uarts_num);
qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", chr);
Expand Down
19 changes: 17 additions & 2 deletions include/hw/arm/aspeed_soc.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -140,6 +140,7 @@ struct AspeedSoCClass {
int wdts_num;
int macs_num;
int uarts_num;
int uarts_base;
const int *irqmap;
const hwaddr *memmap;
uint32_t num_cpus;
Expand All @@ -151,6 +152,7 @@ const char *aspeed_soc_cpu_type(AspeedSoCClass *sc);
enum {
ASPEED_DEV_SPI_BOOT,
ASPEED_DEV_IOMEM,
ASPEED_DEV_UART0,
ASPEED_DEV_UART1,
ASPEED_DEV_UART2,
ASPEED_DEV_UART3,
Expand Down Expand Up @@ -222,8 +224,6 @@ enum {
ASPEED_DEV_FSI2,
};

#define ASPEED_SOC_SPI_BOOT_ADDR 0x0

qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev);
bool aspeed_soc_uart_realize(AspeedSoCState *s, Error **errp);
void aspeed_soc_uart_set_chr(AspeedSoCState *s, int dev, Chardev *chr);
Expand All @@ -235,4 +235,19 @@ void aspeed_mmio_map_unimplemented(AspeedSoCState *s, SysBusDevice *dev,
void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype,
unsigned int count, int unit0);

static inline int aspeed_uart_index(int uart_dev)
{
return uart_dev - ASPEED_DEV_UART0;
}

static inline int aspeed_uart_first(AspeedSoCClass *sc)
{
return aspeed_uart_index(sc->uarts_base);
}

static inline int aspeed_uart_last(AspeedSoCClass *sc)
{
return aspeed_uart_first(sc) + sc->uarts_num - 1;
}

#endif /* ASPEED_SOC_H */

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