Skip to content

Commit

Permalink
target/sparc: Move EDGE* to decodetree
Browse files Browse the repository at this point in the history 
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
  • Loading branch information
@rth7680
rth7680 committed Oct 25, 2023
1 parent da68140 commit b88ce6f
Show file tree
Hide file tree
Showing 2 changed files with 133 additions and 160 deletions.
22 changes: 21 additions & 1 deletion target/sparc/insns.decode
View file
Original file line number Diff line number Diff line change
Expand Up @@ -35,6 +35,9 @@ CALL 01 i:s30
@r_r_ri_cc0 .. rd:5 ...... rs1:5 imm:1 rs2_or_imm:s13 &r_r_ri_cc cc=0
@r_r_ri_cc1 .. rd:5 ...... rs1:5 imm:1 rs2_or_imm:s13 &r_r_ri_cc cc=1

&r_r_r rd rs1 rs2
@r_r_r .. rd:5 ...... rs1:5 . ........ rs2:5 &r_r_r

{
[
STBAR 10 00000 101000 01111 0 0000000000000
Expand Down Expand Up @@ -231,7 +234,24 @@ RESTORE 10 ..... 111101 ..... . ............. @r_r_ri
DONE 10 00000 111110 00000 0 0000000000000
RETRY 10 00001 111110 00000 0 0000000000000

NCP 10 ----- 110110 ----- --------- ----- # v8 CPop1
{
[
EDGE8cc 10 ..... 110110 ..... 0 0000 0000 ..... @r_r_r
EDGE8N 10 ..... 110110 ..... 0 0000 0001 ..... @r_r_r
EDGE8Lcc 10 ..... 110110 ..... 0 0000 0010 ..... @r_r_r
EDGE8LN 10 ..... 110110 ..... 0 0000 0011 ..... @r_r_r
EDGE16cc 10 ..... 110110 ..... 0 0000 0100 ..... @r_r_r
EDGE16N 10 ..... 110110 ..... 0 0000 0101 ..... @r_r_r
EDGE16Lcc 10 ..... 110110 ..... 0 0000 0110 ..... @r_r_r
EDGE16LN 10 ..... 110110 ..... 0 0000 0111 ..... @r_r_r
EDGE32cc 10 ..... 110110 ..... 0 0000 1000 ..... @r_r_r
EDGE32N 10 ..... 110110 ..... 0 0000 1001 ..... @r_r_r
EDGE32Lcc 10 ..... 110110 ..... 0 0000 1010 ..... @r_r_r
EDGE32LN 10 ..... 110110 ..... 0 0000 1011 ..... @r_r_r
]
NCP 10 ----- 110110 ----- --------- ----- # v8 CPop1
}

NCP 10 ----- 110111 ----- --------- ----- # v8 CPop2

##
Expand Down
271 changes: 112 additions & 159 deletions target/sparc/translate.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -2728,93 +2728,6 @@ static void gen_load_trap_state_at_tl(TCGv_ptr r_tsptr)
}
}

static void gen_edge(DisasContext *dc, TCGv dst, TCGv s1, TCGv s2,
int width, bool cc, bool left)
{
TCGv lo1, lo2;
uint64_t amask, tabl, tabr;
int shift, imask, omask;

if (cc) {
tcg_gen_mov_tl(cpu_cc_src, s1);
tcg_gen_mov_tl(cpu_cc_src2, s2);
tcg_gen_sub_tl(cpu_cc_dst, s1, s2);
tcg_gen_movi_i32(cpu_cc_op, CC_OP_SUB);
dc->cc_op = CC_OP_SUB;
}

/* Theory of operation: there are two tables, left and right (not to
be confused with the left and right versions of the opcode). These
are indexed by the low 3 bits of the inputs. To make things "easy",
these tables are loaded into two constants, TABL and TABR below.
The operation index = (input & imask) << shift calculates the index
into the constant, while val = (table >> index) & omask calculates
the value we're looking for. */
switch (width) {
case 8:
imask = 0x7;
shift = 3;
omask = 0xff;
if (left) {
tabl = 0x80c0e0f0f8fcfeffULL;
tabr = 0xff7f3f1f0f070301ULL;
} else {
tabl = 0x0103070f1f3f7fffULL;
tabr = 0xfffefcf8f0e0c080ULL;
}
break;
case 16:
imask = 0x6;
shift = 1;
omask = 0xf;
if (left) {
tabl = 0x8cef;
tabr = 0xf731;
} else {
tabl = 0x137f;
tabr = 0xfec8;
}
break;
case 32:
imask = 0x4;
shift = 0;
omask = 0x3;
if (left) {
tabl = (2 << 2) | 3;
tabr = (3 << 2) | 1;
} else {
tabl = (1 << 2) | 3;
tabr = (3 << 2) | 2;
}
break;
default:
abort();
}

lo1 = tcg_temp_new();
lo2 = tcg_temp_new();
tcg_gen_andi_tl(lo1, s1, imask);
tcg_gen_andi_tl(lo2, s2, imask);
tcg_gen_shli_tl(lo1, lo1, shift);
tcg_gen_shli_tl(lo2, lo2, shift);

tcg_gen_shr_tl(lo1, tcg_constant_tl(tabl), lo1);
tcg_gen_shr_tl(lo2, tcg_constant_tl(tabr), lo2);
tcg_gen_andi_tl(lo1, lo1, omask);
tcg_gen_andi_tl(lo2, lo2, omask);

amask = -8;
if (AM_CHECK(dc)) {
amask &= 0xffffffffULL;
}
tcg_gen_andi_tl(s1, s1, amask);
tcg_gen_andi_tl(s2, s2, amask);

/* Compute dst = (s1 == s2 ? lo1 : lo1 & lo2). */
tcg_gen_and_tl(lo2, lo2, lo1);
tcg_gen_movcond_tl(TCG_COND_EQ, dst, s1, s2, lo1, lo2);
}

static void gen_alignaddr(TCGv dst, TCGv s1, TCGv s2, bool left)
{
TCGv tmp = tcg_temp_new();
Expand Down Expand Up @@ -2877,6 +2790,8 @@ static int extract_qfpreg(DisasContext *dc, int x)
# define avail_64(C) true
# define avail_GL(C) ((C)->def->features & CPU_FEATURE_GL)
# define avail_HYPV(C) ((C)->def->features & CPU_FEATURE_HYPV)
# define avail_VIS1(C) ((C)->def->features & CPU_FEATURE_VIS1)
# define avail_VIS2(C) ((C)->def->features & CPU_FEATURE_VIS2)
#else
# define avail_32(C) true
# define avail_ASR17(C) ((C)->def->features & CPU_FEATURE_ASR17)
Expand All @@ -2887,6 +2802,8 @@ static int extract_qfpreg(DisasContext *dc, int x)
# define avail_64(C) false
# define avail_GL(C) false
# define avail_HYPV(C) false
# define avail_VIS1(C) false
# define avail_VIS2(C) false
#endif

/* Default case for non jump instructions. */
Expand Down Expand Up @@ -4187,6 +4104,113 @@ static bool trans_MULScc(DisasContext *dc, arg_r_r_ri_cc *a)
return do_arith(dc, a, CC_OP_ADD, NULL, NULL, gen_op_mulscc);
}

static bool gen_edge(DisasContext *dc, arg_r_r_r *a,
int width, bool cc, bool left)
{
TCGv dst, s1, s2, lo1, lo2;
uint64_t amask, tabl, tabr;
int shift, imask, omask;

dst = gen_dest_gpr(dc, a->rd);
s1 = gen_load_gpr(dc, a->rs1);
s2 = gen_load_gpr(dc, a->rs2);

if (cc) {
tcg_gen_mov_tl(cpu_cc_src, s1);
tcg_gen_mov_tl(cpu_cc_src2, s2);
tcg_gen_sub_tl(cpu_cc_dst, s1, s2);
tcg_gen_movi_i32(cpu_cc_op, CC_OP_SUB);
dc->cc_op = CC_OP_SUB;
}

/*
* Theory of operation: there are two tables, left and right (not to
* be confused with the left and right versions of the opcode). These
* are indexed by the low 3 bits of the inputs. To make things "easy",
* these tables are loaded into two constants, TABL and TABR below.
* The operation index = (input & imask) << shift calculates the index
* into the constant, while val = (table >> index) & omask calculates
* the value we're looking for.
*/
switch (width) {
case 8:
imask = 0x7;
shift = 3;
omask = 0xff;
if (left) {
tabl = 0x80c0e0f0f8fcfeffULL;
tabr = 0xff7f3f1f0f070301ULL;
} else {
tabl = 0x0103070f1f3f7fffULL;
tabr = 0xfffefcf8f0e0c080ULL;
}
break;
case 16:
imask = 0x6;
shift = 1;
omask = 0xf;
if (left) {
tabl = 0x8cef;
tabr = 0xf731;
} else {
tabl = 0x137f;
tabr = 0xfec8;
}
break;
case 32:
imask = 0x4;
shift = 0;
omask = 0x3;
if (left) {
tabl = (2 << 2) | 3;
tabr = (3 << 2) | 1;
} else {
tabl = (1 << 2) | 3;
tabr = (3 << 2) | 2;
}
break;
default:
abort();
}

lo1 = tcg_temp_new();
lo2 = tcg_temp_new();
tcg_gen_andi_tl(lo1, s1, imask);
tcg_gen_andi_tl(lo2, s2, imask);
tcg_gen_shli_tl(lo1, lo1, shift);
tcg_gen_shli_tl(lo2, lo2, shift);

tcg_gen_shr_tl(lo1, tcg_constant_tl(tabl), lo1);
tcg_gen_shr_tl(lo2, tcg_constant_tl(tabr), lo2);
tcg_gen_andi_tl(lo1, lo1, omask);
tcg_gen_andi_tl(lo2, lo2, omask);

amask = address_mask_i(dc, -8);
tcg_gen_andi_tl(s1, s1, amask);
tcg_gen_andi_tl(s2, s2, amask);

/* Compute dst = (s1 == s2 ? lo1 : lo1 & lo2). */
tcg_gen_and_tl(lo2, lo2, lo1);
tcg_gen_movcond_tl(TCG_COND_EQ, dst, s1, s2, lo1, lo2);

gen_store_gpr(dc, a->rd, dst);
return advance_pc(dc);
}

TRANS(EDGE8cc, VIS1, gen_edge, a, 8, 1, 0)
TRANS(EDGE8Lcc, VIS1, gen_edge, a, 8, 1, 1)
TRANS(EDGE16cc, VIS1, gen_edge, a, 16, 1, 0)
TRANS(EDGE16Lcc, VIS1, gen_edge, a, 16, 1, 1)
TRANS(EDGE32cc, VIS1, gen_edge, a, 32, 1, 0)
TRANS(EDGE32Lcc, VIS1, gen_edge, a, 32, 1, 1)

TRANS(EDGE8N, VIS2, gen_edge, a, 8, 0, 0)
TRANS(EDGE8LN, VIS2, gen_edge, a, 8, 0, 1)
TRANS(EDGE16N, VIS2, gen_edge, a, 16, 0, 0)
TRANS(EDGE16LN, VIS2, gen_edge, a, 16, 0, 1)
TRANS(EDGE32N, VIS2, gen_edge, a, 32, 0, 0)
TRANS(EDGE32LN, VIS2, gen_edge, a, 32, 0, 1)

static bool do_shift_r(DisasContext *dc, arg_shiftr *a, bool l, bool u)
{
TCGv dst, src1, src2;
Expand Down Expand Up @@ -5075,89 +5099,18 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn)

switch (opf) {
case 0x000: /* VIS I edge8cc */
CHECK_FPU_FEATURE(dc, VIS1);
cpu_src1 = gen_load_gpr(dc, rs1);
cpu_src2 = gen_load_gpr(dc, rs2);
gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 8, 1, 0);
gen_store_gpr(dc, rd, cpu_dst);
break;
case 0x001: /* VIS II edge8n */
CHECK_FPU_FEATURE(dc, VIS2);
cpu_src1 = gen_load_gpr(dc, rs1);
cpu_src2 = gen_load_gpr(dc, rs2);
gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 8, 0, 0);
gen_store_gpr(dc, rd, cpu_dst);
break;
case 0x002: /* VIS I edge8lcc */
CHECK_FPU_FEATURE(dc, VIS1);
cpu_src1 = gen_load_gpr(dc, rs1);
cpu_src2 = gen_load_gpr(dc, rs2);
gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 8, 1, 1);
gen_store_gpr(dc, rd, cpu_dst);
break;
case 0x003: /* VIS II edge8ln */
CHECK_FPU_FEATURE(dc, VIS2);
cpu_src1 = gen_load_gpr(dc, rs1);
cpu_src2 = gen_load_gpr(dc, rs2);
gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 8, 0, 1);
gen_store_gpr(dc, rd, cpu_dst);
break;
case 0x004: /* VIS I edge16cc */
CHECK_FPU_FEATURE(dc, VIS1);
cpu_src1 = gen_load_gpr(dc, rs1);
cpu_src2 = gen_load_gpr(dc, rs2);
gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 16, 1, 0);
gen_store_gpr(dc, rd, cpu_dst);
break;
case 0x005: /* VIS II edge16n */
CHECK_FPU_FEATURE(dc, VIS2);
cpu_src1 = gen_load_gpr(dc, rs1);
cpu_src2 = gen_load_gpr(dc, rs2);
gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 16, 0, 0);
gen_store_gpr(dc, rd, cpu_dst);
break;
case 0x006: /* VIS I edge16lcc */
CHECK_FPU_FEATURE(dc, VIS1);
cpu_src1 = gen_load_gpr(dc, rs1);
cpu_src2 = gen_load_gpr(dc, rs2);
gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 16, 1, 1);
gen_store_gpr(dc, rd, cpu_dst);
break;
case 0x007: /* VIS II edge16ln */
CHECK_FPU_FEATURE(dc, VIS2);
cpu_src1 = gen_load_gpr(dc, rs1);
cpu_src2 = gen_load_gpr(dc, rs2);
gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 16, 0, 1);
gen_store_gpr(dc, rd, cpu_dst);
break;
case 0x008: /* VIS I edge32cc */
CHECK_FPU_FEATURE(dc, VIS1);
cpu_src1 = gen_load_gpr(dc, rs1);
cpu_src2 = gen_load_gpr(dc, rs2);
gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 32, 1, 0);
gen_store_gpr(dc, rd, cpu_dst);
break;
case 0x009: /* VIS II edge32n */
CHECK_FPU_FEATURE(dc, VIS2);
cpu_src1 = gen_load_gpr(dc, rs1);
cpu_src2 = gen_load_gpr(dc, rs2);
gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 32, 0, 0);
gen_store_gpr(dc, rd, cpu_dst);
break;
case 0x00a: /* VIS I edge32lcc */
CHECK_FPU_FEATURE(dc, VIS1);
cpu_src1 = gen_load_gpr(dc, rs1);
cpu_src2 = gen_load_gpr(dc, rs2);
gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 32, 1, 1);
gen_store_gpr(dc, rd, cpu_dst);
break;
case 0x00b: /* VIS II edge32ln */
CHECK_FPU_FEATURE(dc, VIS2);
cpu_src1 = gen_load_gpr(dc, rs1);
cpu_src2 = gen_load_gpr(dc, rs2);
gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 32, 0, 1);
gen_store_gpr(dc, rd, cpu_dst);
break;
g_assert_not_reached(); /* in decodetree */
case 0x010: /* VIS I array8 */
CHECK_FPU_FEATURE(dc, VIS1);
cpu_src1 = gen_load_gpr(dc, rs1);
Expand Down

0 comments on commit b88ce6f

Please sign in to comment.