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Merge remote-tracking branch 'remotes/palmer/tags/riscv-for-master-5.…
…0-sf1' into staging RISC-V Patches for the 5.0 Soft Freeze, Part 1 This patch set contains a handful of collected fixes that I'd like to target for the 5.0 soft freeze (I know that's a long way away, I just don't know what else to call these): * A fix for a memory leak initializing the sifive_u board. * Fixes to privilege mode emulation related to interrupts and fstatus. Notably absent is the H extension implementation. That's pretty much reviewed, but not quite ready to go yet and I didn't want to hold back these important fixes. This boots 32-bit and 64-bit Linux (buildroot this time, just for fun) and passes "make check". # gpg: Signature made Tue 21 Jan 2020 22:55:28 GMT # gpg: using RSA key 2B3C3747446843B24A943A7A2E1319F35FBB1889 # gpg: issuer "palmer@dabbelt.com" # gpg: Good signature from "Palmer Dabbelt <palmer@dabbelt.com>" [unknown] # gpg: aka "Palmer Dabbelt <palmer@sifive.com>" [unknown] # gpg: aka "Palmer Dabbelt <palmerdabbelt@google.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 00CE 76D1 8349 60DF CE88 6DF8 EF4C A150 2CCB AB41 # Subkey fingerprint: 2B3C 3747 4468 43B2 4A94 3A7A 2E13 19F3 5FBB 1889 * remotes/palmer/tags/riscv-for-master-5.0-sf1: target/riscv: update mstatus.SD when FS is set dirty target/riscv: fsd/fsw doesn't dirty FP state target/riscv: Fix tb->flags FS status riscv: Set xPIE to 1 after xRET riscv/sifive_u: fix a memory leak in soc_realize() Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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