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target/riscv: hardwire bits in hideleg and hedeleg
The specification mandates for certain bits to be hardwired in the hypervisor delegation registers. This was not being enforced. Signed-off-by: Jose Martins <josemartins90@gmail.com> Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210522155902.374439-1-josemartins90@gmail.com [ Changes by AF: - Improve indentation - Convert delegable_excps to a #define to avoid failures with GCC 8 ] Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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