Skip to content

Commit

Permalink
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-2…
Browse files Browse the repository at this point in the history 
…0180215-1' into staging

target-arm queue:
 * aspeed: code cleanup to use unimplemented_device
 * preparatory work for 'raspi3' RaspberryPi 3 machine model
 * more SVE prep work
 * v8M: add minor missing registers
 * v7M: fix bug where we weren't migrating v7m.other_sp
 * v7M: fix bugs in handling of interrupt registers for
   external interrupts beyond 32

# gpg: Signature made Thu 15 Feb 2018 18:34:40 GMT
# gpg:                using RSA key 3C2525ED14360CDE
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>"
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>"
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20180215-1:
  raspi: Raspberry Pi 3 support
  bcm2836: Make CPU type configurable
  target/arm: Implement v8M MSPLIM and PSPLIM registers
  target/arm: Migrate v7m.other_sp
  target/arm: Add AIRCR to vmstate struct
  hw/intc/armv7m_nvic: Fix byte-to-interrupt number conversions
  target/arm: Implement writing to CONTROL_NS for v8M
  hw/intc/armv7m_nvic: Implement SCR
  hw/intc/armv7m_nvic: Implement cache ID registers
  hw/intc/armv7m_nvic: Implement v8M CPPWR register
  hw/intc/armv7m_nvic: Implement M profile cache maintenance ops
  hw/intc/armv7m_nvic: Fix ICSR PENDNMISET/CLR handling
  hw/intc/armv7m_nvic: Don't hardcode M profile ID registers in NVIC
  target/arm: Handle SVE registers when using clear_vec_high
  target/arm: Enforce access to ZCR_EL at translation
  target/arm: Suppress TB end for FPCR/FPSR
  target/arm: Enforce FP access to FPCR/FPSR
  target/arm: Remove ARM_CP_64BIT from ZCR_EL registers
  hw/arm/aspeed: simplify using the 'unimplemented device' for aspeed_soc.io
  hw/arm/aspeed: directly map the serial device to the system address space

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
  • Loading branch information
@pm215
pm215 committed Feb 15, 2018
2 parents f003d07 + bade581 commit cc5a0ae
Show file tree
Hide file tree
Showing 12 changed files with 429 additions and 211 deletions.
35 changes: 5 additions & 30 deletions hw/arm/aspeed_soc.c
View file
Expand Up @@ -15,6 +15,7 @@
#include "qemu-common.h"
#include "cpu.h"
#include "exec/address-spaces.h"
#include "hw/misc/unimp.h"
#include "hw/arm/aspeed_soc.h"
#include "hw/char/serial.h"
#include "qemu/log.h"
Expand Down Expand Up @@ -99,31 +100,6 @@ static const AspeedSoCInfo aspeed_socs[] = {
},
};

/*
* IO handlers: simply catch any reads/writes to IO addresses that aren't
* handled by a device mapping.
*/

static uint64_t aspeed_soc_io_read(void *p, hwaddr offset, unsigned size)
{
qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx " [%u]\n",
__func__, offset, size);
return 0;
}

static void aspeed_soc_io_write(void *opaque, hwaddr offset, uint64_t value,
unsigned size)
{
qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx " <- 0x%" PRIx64 " [%u]\n",
__func__, offset, value, size);
}

static const MemoryRegionOps aspeed_soc_io_ops = {
.read = aspeed_soc_io_read,
.write = aspeed_soc_io_write,
.endianness = DEVICE_LITTLE_ENDIAN,
};

static void aspeed_soc_init(Object *obj)
{
AspeedSoCState *s = ASPEED_SOC(obj);
Expand Down Expand Up @@ -199,10 +175,8 @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
Error *err = NULL, *local_err = NULL;

/* IO space */
memory_region_init_io(&s->iomem, NULL, &aspeed_soc_io_ops, NULL,
"aspeed_soc.io", ASPEED_SOC_IOMEM_SIZE);
memory_region_add_subregion_overlap(get_system_memory(),
ASPEED_SOC_IOMEM_BASE, &s->iomem, -1);
create_unimplemented_device("aspeed_soc.io",
ASPEED_SOC_IOMEM_BASE, ASPEED_SOC_IOMEM_SIZE);

/* CPU */
object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err);
Expand Down Expand Up @@ -257,7 +231,8 @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
/* UART - attach an 8250 to the IO space as our UART5 */
if (serial_hds[0]) {
qemu_irq uart5 = qdev_get_gpio_in(DEVICE(&s->vic), uart_irqs[4]);
serial_mm_init(&s->iomem, ASPEED_SOC_UART_5_BASE, 2,
serial_mm_init(get_system_memory(),
ASPEED_SOC_IOMEM_BASE + ASPEED_SOC_UART_5_BASE, 2,
uart5, 38400, serial_hds[0], DEVICE_LITTLE_ENDIAN);
}

Expand Down
17 changes: 9 additions & 8 deletions hw/arm/bcm2836.c
View file
Expand Up @@ -26,14 +26,6 @@
static void bcm2836_init(Object *obj)
{
BCM2836State *s = BCM2836(obj);
int n;

for (n = 0; n < BCM2836_NCPUS; n++) {
object_initialize(&s->cpus[n], sizeof(s->cpus[n]),
"cortex-a15-" TYPE_ARM_CPU);
object_property_add_child(obj, "cpu[*]", OBJECT(&s->cpus[n]),
&error_abort);
}

object_initialize(&s->control, sizeof(s->control), TYPE_BCM2836_CONTROL);
object_property_add_child(obj, "control", OBJECT(&s->control), NULL);
Expand All @@ -59,6 +51,14 @@ static void bcm2836_realize(DeviceState *dev, Error **errp)

/* common peripherals from bcm2835 */

obj = OBJECT(dev);
for (n = 0; n < BCM2836_NCPUS; n++) {
object_initialize(&s->cpus[n], sizeof(s->cpus[n]),
s->cpu_type);
object_property_add_child(obj, "cpu[*]", OBJECT(&s->cpus[n]),
&error_abort);
}

obj = object_property_get_link(OBJECT(dev), "ram", &err);
if (obj == NULL) {
error_setg(errp, "%s: required ram link not found: %s",
Expand Down Expand Up @@ -150,6 +150,7 @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
}

static Property bcm2836_props[] = {
DEFINE_PROP_STRING("cpu-type", BCM2836State, cpu_type),
DEFINE_PROP_UINT32("enabled-cpus", BCM2836State, enabled_cpus, BCM2836_NCPUS),
DEFINE_PROP_END_OF_LIST()
};
Expand Down
34 changes: 24 additions & 10 deletions hw/arm/raspi.c
View file
Expand Up @@ -5,6 +5,9 @@
* Rasperry Pi 2 emulation Copyright (c) 2015, Microsoft
* Written by Andrew Baumann
*
* Raspberry Pi 3 emulation Copyright (c) 2018 Zoltán Baldaszti
* Upstream code cleanup (c) 2018 Pekka Enberg
*
* This code is licensed under the GNU GPLv2 and later.
*/

Expand All @@ -22,10 +25,11 @@
#define SMPBOOT_ADDR 0x300 /* this should leave enough space for ATAGS */
#define MVBAR_ADDR 0x400 /* secure vectors */
#define BOARDSETUP_ADDR (MVBAR_ADDR + 0x20) /* board setup code */
#define FIRMWARE_ADDR 0x8000 /* Pi loads kernel.img here by default */
#define FIRMWARE_ADDR_2 0x8000 /* Pi 2 loads kernel.img here by default */
#define FIRMWARE_ADDR_3 0x80000 /* Pi 3 loads kernel.img here by default */

/* Table of Linux board IDs for different Pi versions */
static const int raspi_boardid[] = {[1] = 0xc42, [2] = 0xc43};
static const int raspi_boardid[] = {[1] = 0xc42, [2] = 0xc43, [3] = 0xc44};

typedef struct RasPiState {
BCM2836State soc;
Expand Down Expand Up @@ -83,8 +87,8 @@ static void setup_boot(MachineState *machine, int version, size_t ram_size)
binfo.secure_board_setup = true;
binfo.secure_boot = true;

/* Pi2 requires SMP setup */
if (version == 2) {
/* Pi2 and Pi3 requires SMP setup */
if (version >= 2) {
binfo.smp_loader_start = SMPBOOT_ADDR;
binfo.write_secondary_boot = write_smpboot;
binfo.secondary_cpu_reset_hook = reset_secondary;
Expand All @@ -94,15 +98,16 @@ static void setup_boot(MachineState *machine, int version, size_t ram_size)
* the normal Linux boot process
*/
if (machine->firmware) {
hwaddr firmware_addr = version == 3 ? FIRMWARE_ADDR_3 : FIRMWARE_ADDR_2;
/* load the firmware image (typically kernel.img) */
r = load_image_targphys(machine->firmware, FIRMWARE_ADDR,
ram_size - FIRMWARE_ADDR);
r = load_image_targphys(machine->firmware, firmware_addr,
ram_size - firmware_addr);
if (r < 0) {
error_report("Failed to load firmware from %s", machine->firmware);
exit(1);
}

binfo.entry = FIRMWARE_ADDR;
binfo.entry = firmware_addr;
binfo.firmware_loaded = true;
} else {
binfo.kernel_filename = machine->kernel_filename;
Expand All @@ -113,7 +118,7 @@ static void setup_boot(MachineState *machine, int version, size_t ram_size)
arm_load_kernel(ARM_CPU(first_cpu), &binfo);
}

static void raspi2_init(MachineState *machine)
static void raspi_init(MachineState *machine, int version)
{
RasPiState *s = g_new0(RasPiState, 1);
uint32_t vcram_size;
Expand All @@ -135,9 +140,12 @@ static void raspi2_init(MachineState *machine)
/* Setup the SOC */
object_property_add_const_link(OBJECT(&s->soc), "ram", OBJECT(&s->ram),
&error_abort);
object_property_set_str(OBJECT(&s->soc), machine->cpu_type, "cpu-type",
&error_abort);
object_property_set_int(OBJECT(&s->soc), smp_cpus, "enabled-cpus",
&error_abort);
object_property_set_int(OBJECT(&s->soc), 0xa21041, "board-rev",
int board_rev = version == 3 ? 0xa02082 : 0xa21041;
object_property_set_int(OBJECT(&s->soc), board_rev, "board-rev",
&error_abort);
object_property_set_bool(OBJECT(&s->soc), true, "realized", &error_abort);

Expand All @@ -155,7 +163,12 @@ static void raspi2_init(MachineState *machine)

vcram_size = object_property_get_uint(OBJECT(&s->soc), "vcram-size",
&error_abort);
setup_boot(machine, 2, machine->ram_size - vcram_size);
setup_boot(machine, version, machine->ram_size - vcram_size);
}

static void raspi2_init(MachineState *machine)
{
raspi_init(machine, 2);
}

static void raspi2_machine_init(MachineClass *mc)
Expand All @@ -166,6 +179,7 @@ static void raspi2_machine_init(MachineClass *mc)
mc->no_parallel = 1;
mc->no_floppy = 1;
mc->no_cdrom = 1;
mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15");
mc->max_cpus = BCM2836_NCPUS;
mc->min_cpus = BCM2836_NCPUS;
mc->default_cpus = BCM2836_NCPUS;
Expand Down

0 comments on commit cc5a0ae

Please sign in to comment.