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Use f-strings in python scripts
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Replace python 2 format string with f-strings

Signed-off-by: Marco Liebel <quic_mliebel@quicinc.com>
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Taylor Simpson <tsimpson@quicinc.com>
Tested-by: Taylor Simpson <tsimpson@quicinc.com>
Message-Id: <20230320092533.2859433-2-quic_mliebel@quicinc.com>
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Marco Liebel authored and taylorsimpson committed Apr 21, 2023
1 parent bee1fc5 commit cd6c4ed
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Showing 12 changed files with 250 additions and 306 deletions.
115 changes: 45 additions & 70 deletions target/hexagon/gen_analyze_funcs.py
Original file line number Diff line number Diff line change
Expand Up @@ -29,57 +29,49 @@ def is_predicated(tag):
return 'A_CONDEXEC' in hex_common.attribdict[tag]

def analyze_opn_old(f, tag, regtype, regid, regno):
regN = "%s%sN" % (regtype, regid)
regN = f"{regtype}{regid}N"
predicated = "true" if is_predicated(tag) else "false"
if (regtype == "R"):
if (regid in {"ss", "tt"}):
f.write("// const int %s = insn->regno[%d];\n" % \
(regN, regno))
f.write(f"// const int {regN} = insn->regno[{regno}];\n")
elif (regid in {"dd", "ee", "xx", "yy"}):
f.write(" const int %s = insn->regno[%d];\n" % (regN, regno))
f.write(" ctx_log_reg_write_pair(ctx, %s, %s);\n" % \
(regN, predicated))
f.write(f" const int {regN} = insn->regno[{regno}];\n")
f.write(f" ctx_log_reg_write_pair(ctx, {regN}, {predicated});\n")
elif (regid in {"s", "t", "u", "v"}):
f.write("// const int %s = insn->regno[%d];\n" % \
(regN, regno))
f.write(f"// const int {regN} = insn->regno[{regno}];\n")
elif (regid in {"d", "e", "x", "y"}):
f.write(" const int %s = insn->regno[%d];\n" % (regN, regno))
f.write(" ctx_log_reg_write(ctx, %s, %s);\n" % \
(regN, predicated))
f.write(f" const int {regN} = insn->regno[{regno}];\n")
f.write(f" ctx_log_reg_write(ctx, {regN}, {predicated});\n")
else:
print("Bad register parse: ", regtype, regid)
elif (regtype == "P"):
if (regid in {"s", "t", "u", "v"}):
f.write("// const int %s = insn->regno[%d];\n" % \
(regN, regno))
f.write(f"// const int {regN} = insn->regno[{regno}];\n")
elif (regid in {"d", "e", "x"}):
f.write(" const int %s = insn->regno[%d];\n" % (regN, regno))
f.write(" ctx_log_pred_write(ctx, %s);\n" % (regN))
f.write(f" const int {regN} = insn->regno[{regno}];\n")
f.write(f" ctx_log_pred_write(ctx, {regN});\n")
else:
print("Bad register parse: ", regtype, regid)
elif (regtype == "C"):
if (regid == "ss"):
f.write("// const int %s = insn->regno[%d] + HEX_REG_SA0;\n" % \
(regN, regno))
f.write(f"// const int {regN} = insn->regno[{regno}] "
"+ HEX_REG_SA0;\n")
elif (regid == "dd"):
f.write(" const int %s = insn->regno[%d] + HEX_REG_SA0;\n" % \
(regN, regno))
f.write(" ctx_log_reg_write_pair(ctx, %s, %s);\n" % \
(regN, predicated))
f.write(f" const int {regN} = insn->regno[{regno}] "
"+ HEX_REG_SA0;\n")
f.write(f" ctx_log_reg_write_pair(ctx, {regN}, {predicated});\n")
elif (regid == "s"):
f.write("// const int %s = insn->regno[%d] + HEX_REG_SA0;\n" % \
(regN, regno))
f.write(f"// const int {regN} = insn->regno[{regno}] "
"+ HEX_REG_SA0;\n")
elif (regid == "d"):
f.write(" const int %s = insn->regno[%d] + HEX_REG_SA0;\n" % \
(regN, regno))
f.write(" ctx_log_reg_write(ctx, %s, %s);\n" % \
(regN, predicated))
f.write(f" const int {regN} = insn->regno[{regno}] "
"+ HEX_REG_SA0;\n")
f.write(f" ctx_log_reg_write(ctx, {regN}, {predicated});\n")
else:
print("Bad register parse: ", regtype, regid)
elif (regtype == "M"):
if (regid == "u"):
f.write("// const int %s = insn->regno[%d];\n"% \
(regN, regno))
f.write(f"// const int {regN} = insn->regno[{regno}];\n")
else:
print("Bad register parse: ", regtype, regid)
elif (regtype == "V"):
Expand All @@ -89,84 +81,67 @@ def analyze_opn_old(f, tag, regtype, regid, regno):
elif (hex_common.is_tmp_result(tag)):
newv = "EXT_TMP"
if (regid in {"dd", "xx"}):
f.write(" const int %s = insn->regno[%d];\n" %\
(regN, regno))
f.write(" ctx_log_vreg_write_pair(ctx, %s, %s, %s);\n" % \
(regN, newv, predicated))
f.write(f" const int {regN} = insn->regno[{regno}];\n")
f.write(f" ctx_log_vreg_write_pair(ctx, {regN}, {newv}, "
f"{predicated});\n")
elif (regid in {"uu", "vv"}):
f.write("// const int %s = insn->regno[%d];\n" % \
(regN, regno))
f.write(f"// const int {regN} = insn->regno[{regno}];\n")
elif (regid in {"s", "u", "v", "w"}):
f.write("// const int %s = insn->regno[%d];\n" % \
(regN, regno))
f.write(f"// const int {regN} = insn->regno[{regno}];\n")
elif (regid in {"d", "x", "y"}):
f.write(" const int %s = insn->regno[%d];\n" % \
(regN, regno))
f.write(" ctx_log_vreg_write(ctx, %s, %s, %s);\n" % \
(regN, newv, predicated))
f.write(f" const int {regN} = insn->regno[{regno}];\n")
f.write(f" ctx_log_vreg_write(ctx, {regN}, {newv}, "
f"{predicated});\n")
else:
print("Bad register parse: ", regtype, regid)
elif (regtype == "Q"):
if (regid in {"d", "e", "x"}):
f.write(" const int %s = insn->regno[%d];\n" % \
(regN, regno))
f.write(" ctx_log_qreg_write(ctx, %s);\n" % (regN))
f.write(f" const int {regN} = insn->regno[{regno}];\n")
f.write(f" ctx_log_qreg_write(ctx, {regN});\n")
elif (regid in {"s", "t", "u", "v"}):
f.write("// const int %s = insn->regno[%d];\n" % \
(regN, regno))
f.write(f"// const int {regN} = insn->regno[{regno}];\n")
else:
print("Bad register parse: ", regtype, regid)
elif (regtype == "G"):
if (regid in {"dd"}):
f.write("// const int %s = insn->regno[%d];\n" % \
(regN, regno))
f.write(f"// const int {regN} = insn->regno[{regno}];\n")
elif (regid in {"d"}):
f.write("// const int %s = insn->regno[%d];\n" % \
(regN, regno))
f.write(f"// const int {regN} = insn->regno[{regno}];\n")
elif (regid in {"ss"}):
f.write("// const int %s = insn->regno[%d];\n" % \
(regN, regno))
f.write(f"// const int {regN} = insn->regno[{regno}];\n")
elif (regid in {"s"}):
f.write("// const int %s = insn->regno[%d];\n" % \
(regN, regno))
f.write(f"// const int {regN} = insn->regno[{regno}];\n")
else:
print("Bad register parse: ", regtype, regid)
elif (regtype == "S"):
if (regid in {"dd"}):
f.write("// const int %s = insn->regno[%d];\n" % \
(regN, regno))
f.write(f"// const int {regN} = insn->regno[{regno}];\n")
elif (regid in {"d"}):
f.write("// const int %s = insn->regno[%d];\n" % \
(regN, regno))
f.write(f"// const int {regN} = insn->regno[{regno}];\n")
elif (regid in {"ss"}):
f.write("// const int %s = insn->regno[%d];\n" % \
(regN, regno))
f.write(f"// const int {regN} = insn->regno[{regno}];\n")
elif (regid in {"s"}):
f.write("// const int %s = insn->regno[%d];\n" % \
(regN, regno))
f.write(f"// const int {regN} = insn->regno[{regno}];\n")
else:
print("Bad register parse: ", regtype, regid)
else:
print("Bad register parse: ", regtype, regid)

def analyze_opn_new(f, tag, regtype, regid, regno):
regN = "%s%sN" % (regtype, regid)
regN = f"{regtype}{regid}N"
if (regtype == "N"):
if (regid in {"s", "t"}):
f.write("// const int %s = insn->regno[%d];\n" % \
(regN, regno))
f.write(f"// const int {regN} = insn->regno[{regno}];\n")
else:
print("Bad register parse: ", regtype, regid)
elif (regtype == "P"):
if (regid in {"t", "u", "v"}):
f.write("// const int %s = insn->regno[%d];\n" % \
(regN, regno))
f.write(f"// const int {regN} = insn->regno[{regno}];\n")
else:
print("Bad register parse: ", regtype, regid)
elif (regtype == "O"):
if (regid == "s"):
f.write("// const int %s = insn->regno[%d];\n" % \
(regN, regno))
f.write(f"// const int {regN} = insn->regno[{regno}];\n")
else:
print("Bad register parse: ", regtype, regid)
else:
Expand Down Expand Up @@ -199,7 +174,7 @@ def analyze_opn(f, tag, regtype, regid, toss, numregs, i):
## }
##
def gen_analyze_func(f, tag, regs, imms):
f.write("static void analyze_%s(DisasContext *ctx)\n" %tag)
f.write(f"static void analyze_{tag}(DisasContext *ctx)\n")
f.write('{\n')

f.write(" Insn *insn G_GNUC_UNUSED = ctx->insn;\n")
Expand Down
54 changes: 26 additions & 28 deletions target/hexagon/gen_helper_funcs.py
Original file line number Diff line number Diff line change
Expand Up @@ -38,23 +38,23 @@ def gen_helper_return_type_pair(f,regtype,regid,regno):

def gen_helper_arg(f,regtype,regid,regno):
if regno > 0 : f.write(", " )
f.write("int32_t %s%sV" % (regtype,regid))
f.write(f"int32_t {regtype}{regid}V")

def gen_helper_arg_new(f,regtype,regid,regno):
if regno >= 0 : f.write(", " )
f.write("int32_t %s%sN" % (regtype,regid))
f.write(f"int32_t {regtype}{regid}N")

def gen_helper_arg_pair(f,regtype,regid,regno):
if regno >= 0 : f.write(", ")
f.write("int64_t %s%sV" % (regtype,regid))
f.write(f"int64_t {regtype}{regid}V")

def gen_helper_arg_ext(f,regtype,regid,regno):
if regno > 0 : f.write(", ")
f.write("void *%s%sV_void" % (regtype,regid))
f.write(f"void *{regtype}{regid}V_void")

def gen_helper_arg_ext_pair(f,regtype,regid,regno):
if regno > 0 : f.write(", ")
f.write("void *%s%sV_void" % (regtype,regid))
f.write(f"void *{regtype}{regid}V_void")

def gen_helper_arg_opn(f,regtype,regid,i,tag):
if (hex_common.is_pair(regid)):
Expand All @@ -76,27 +76,25 @@ def gen_helper_arg_opn(f,regtype,regid,i,tag):
print("Bad register parse: ",regtype,regid,toss,numregs)

def gen_helper_arg_imm(f,immlett):
f.write(", int32_t %s" % (hex_common.imm_name(immlett)))
f.write(f", int32_t {hex_common.imm_name(immlett)}")

def gen_helper_dest_decl(f,regtype,regid,regno,subfield=""):
f.write(" int32_t %s%sV%s = 0;\n" % \
(regtype,regid,subfield))
f.write(f" int32_t {regtype}{regid}V{subfield} = 0;\n")

def gen_helper_dest_decl_pair(f,regtype,regid,regno,subfield=""):
f.write(" int64_t %s%sV%s = 0;\n" % \
(regtype,regid,subfield))
f.write(f" int64_t {regtype}{regid}V{subfield} = 0;\n")

def gen_helper_dest_decl_ext(f,regtype,regid):
if (regtype == "Q"):
f.write(" /* %s%sV is *(MMQReg *)(%s%sV_void) */\n" % \
(regtype,regid,regtype,regid))
f.write(f" /* {regtype}{regid}V is *(MMQReg *)"
f"({regtype}{regid}V_void) */\n")
else:
f.write(" /* %s%sV is *(MMVector *)(%s%sV_void) */\n" % \
(regtype,regid,regtype,regid))
f.write(f" /* {regtype}{regid}V is *(MMVector *)"
f"({regtype}{regid}V_void) */\n")

def gen_helper_dest_decl_ext_pair(f,regtype,regid,regno):
f.write(" /* %s%sV is *(MMVectorPair *))%s%sV_void) */\n" % \
(regtype,regid,regtype, regid))
f.write(f" /* {regtype}{regid}V is *(MMVectorPair *))"
f"{regtype}{regid}V_void) */\n")

def gen_helper_dest_decl_opn(f,regtype,regid,i):
if (hex_common.is_pair(regid)):
Expand All @@ -114,21 +112,21 @@ def gen_helper_dest_decl_opn(f,regtype,regid,i):

def gen_helper_src_var_ext(f,regtype,regid):
if (regtype == "Q"):
f.write(" /* %s%sV is *(MMQReg *)(%s%sV_void) */\n" % \
(regtype,regid,regtype,regid))
f.write(f" /* {regtype}{regid}V is *(MMQReg *)"
f"({regtype}{regid}V_void) */\n")
else:
f.write(" /* %s%sV is *(MMVector *)(%s%sV_void) */\n" % \
(regtype,regid,regtype,regid))
f.write(f" /* {regtype}{regid}V is *(MMVector *)"
f"({regtype}{regid}V_void) */\n")

def gen_helper_src_var_ext_pair(f,regtype,regid,regno):
f.write(" /* %s%sV%s is *(MMVectorPair *)(%s%sV%s_void) */\n" % \
(regtype,regid,regno,regtype,regid,regno))
f.write(f" /* {regtype}{regid}V{regno} is *(MMVectorPair *)"
f"({regtype}{regid}V{regno}_void) */\n")

def gen_helper_return(f,regtype,regid,regno):
f.write(" return %s%sV;\n" % (regtype,regid))
f.write(f" return {regtype}{regid}V;\n")

def gen_helper_return_pair(f,regtype,regid,regno):
f.write(" return %s%sV;\n" % (regtype,regid))
f.write(f" return {regtype}{regid}V;\n")

def gen_helper_dst_write_ext(f,regtype,regid):
return
Expand Down Expand Up @@ -181,8 +179,8 @@ def gen_helper_function(f, tag, tagregs, tagimms):

if (numscalarresults > 1):
## The helper is bogus when there is more than one result
f.write("void HELPER(%s)(CPUHexagonState *env) { BOGUS_HELPER(%s); }\n"
% (tag, tag))
f.write(f"void HELPER({tag})(CPUHexagonState *env) "
f"{{ BOGUS_HELPER({tag}); }}\n")
else:
## The return type of the function is the type of the destination
## register (if scalar)
Expand All @@ -205,7 +203,7 @@ def gen_helper_function(f, tag, tagregs, tagimms):

if (numscalarresults == 0):
f.write("void")
f.write(" HELPER(%s)(CPUHexagonState *env" % tag)
f.write(f" HELPER({tag})(CPUHexagonState *env")

## Arguments include the vector destination operands
i = 1
Expand Down Expand Up @@ -290,7 +288,7 @@ def gen_helper_function(f, tag, tagregs, tagimms):
if 'A_FPOP' in hex_common.attribdict[tag]:
f.write(' arch_fpop_start(env);\n');

f.write(" %s\n" % hex_common.semdict[tag])
f.write(f" {hex_common.semdict[tag]}\n")

if 'A_FPOP' in hex_common.attribdict[tag]:
f.write(' arch_fpop_end(env);\n');
Expand Down
10 changes: 5 additions & 5 deletions target/hexagon/gen_helper_protos.py
Original file line number Diff line number Diff line change
Expand Up @@ -47,9 +47,9 @@

def gen_def_helper_opn(f, tag, regtype, regid, toss, numregs, i):
if (hex_common.is_pair(regid)):
f.write(", %s" % (def_helper_types_pair[regtype]))
f.write(f", {def_helper_types_pair[regtype]}")
elif (hex_common.is_single(regid)):
f.write(", %s" % (def_helper_types[regtype]))
f.write(f", {def_helper_types[regtype]}")
else:
print("Bad register parse: ",regtype,regid,toss,numregs)

Expand Down Expand Up @@ -77,7 +77,7 @@ def gen_helper_prototype(f, tag, tagregs, tagimms):

if (numscalarresults > 1):
## The helper is bogus when there is more than one result
f.write('DEF_HELPER_1(%s, void, env)\n' % tag)
f.write(f'DEF_HELPER_1({tag}, void, env)\n')
else:
## Figure out how many arguments the helper will take
if (numscalarresults == 0):
Expand All @@ -88,7 +88,7 @@ def gen_helper_prototype(f, tag, tagregs, tagimms):
if hex_common.need_PC(tag): def_helper_size += 1
if hex_common.helper_needs_next_PC(tag): def_helper_size += 1
if hex_common.need_condexec_reg(tag, regs): def_helper_size += 1
f.write('DEF_HELPER_%s(%s' % (def_helper_size, tag))
f.write(f'DEF_HELPER_{def_helper_size}({tag}')
## The return type is void
f.write(', void' )
else:
Expand All @@ -99,7 +99,7 @@ def gen_helper_prototype(f, tag, tagregs, tagimms):
if hex_common.need_PC(tag): def_helper_size += 1
if hex_common.need_condexec_reg(tag, regs): def_helper_size += 1
if hex_common.helper_needs_next_PC(tag): def_helper_size += 1
f.write('DEF_HELPER_%s(%s' % (def_helper_size, tag))
f.write(f'DEF_HELPER_{def_helper_size}({tag}')

## Generate the qemu DEF_HELPER type for each result
## Iterate over this list twice
Expand Down
10 changes: 5 additions & 5 deletions target/hexagon/gen_idef_parser_funcs.py
Original file line number Diff line number Diff line change
@@ -1,7 +1,7 @@
#!/usr/bin/env python3

##
## Copyright(c) 2019-2022 rev.ng Labs Srl. All Rights Reserved.
## Copyright(c) 2019-2023 rev.ng Labs Srl. All Rights Reserved.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
Expand Down Expand Up @@ -110,20 +110,20 @@ def main():
and hex_common.is_new_val(regtype, regid, tag))

if is_pair or is_single_old:
arguments.append("%s%s%sV" % (prefix, regtype, regid))
arguments.append(f"{prefix}{regtype}{regid}V")
elif is_single_new:
arguments.append("%s%s%sN" % (prefix, regtype, regid))
arguments.append(f"{prefix}{regtype}{regid}N")
else:
print("Bad register parse: ",regtype,regid,toss,numregs)

for immlett,bits,immshift in imms:
arguments.append(hex_common.imm_name(immlett))

f.write("%s(%s) {\n" % (tag, ", ".join(arguments)))
f.write(f"{tag}({', '.join(arguments)}) {{\n")
f.write(" ");
if hex_common.need_ea(tag):
f.write("size4u_t EA; ");
f.write("%s\n" % hex_common.semdict[tag])
f.write(f"{hex_common.semdict[tag]}\n")
f.write("}\n\n")

if __name__ == "__main__":
Expand Down

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