Skip to content

Commit

Permalink
target/loongarch: Implement vinsgr2vr vpickve2gr vreplgr2vr
Browse files Browse the repository at this point in the history 
This patch includes:
- VINSGR2VR.{B/H/W/D};
- VPICKVE2GR.{B/H/W/D}[U];
- VREPLGR2VR.{B/H/W/D}.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20230504122810.4094787-39-gaosong@loongson.cn>
  • Loading branch information
@gaosong-loongson
gaosong-loongson committed May 6, 2023
1 parent d0dfa19 commit cdbdefb
Show file tree
Hide file tree
Showing 3 changed files with 173 additions and 0 deletions.
33 changes: 33 additions & 0 deletions target/loongarch/disas.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -818,6 +818,21 @@ static void output_vvvv(DisasContext *ctx, arg_vvvv *a, const char *mnemonic)
output(ctx, mnemonic, "v%d, v%d, v%d, v%d", a->vd, a->vj, a->vk, a->va);
}

static void output_vr_i(DisasContext *ctx, arg_vr_i *a, const char *mnemonic)
{
output(ctx, mnemonic, "v%d, r%d, 0x%x", a->vd, a->rj, a->imm);
}

static void output_rv_i(DisasContext *ctx, arg_rv_i *a, const char *mnemonic)
{
output(ctx, mnemonic, "r%d, v%d, 0x%x", a->rd, a->vj, a->imm);
}

static void output_vr(DisasContext *ctx, arg_vr *a, const char *mnemonic)
{
output(ctx, mnemonic, "v%d, r%d", a->vd, a->rj);
}

INSN_LSX(vadd_b, vvv)
INSN_LSX(vadd_h, vvv)
INSN_LSX(vadd_w, vvv)
Expand Down Expand Up @@ -1561,3 +1576,21 @@ INSN_LSX(vsetallnez_b, cv)
INSN_LSX(vsetallnez_h, cv)
INSN_LSX(vsetallnez_w, cv)
INSN_LSX(vsetallnez_d, cv)

INSN_LSX(vinsgr2vr_b, vr_i)
INSN_LSX(vinsgr2vr_h, vr_i)
INSN_LSX(vinsgr2vr_w, vr_i)
INSN_LSX(vinsgr2vr_d, vr_i)
INSN_LSX(vpickve2gr_b, rv_i)
INSN_LSX(vpickve2gr_h, rv_i)
INSN_LSX(vpickve2gr_w, rv_i)
INSN_LSX(vpickve2gr_d, rv_i)
INSN_LSX(vpickve2gr_bu, rv_i)
INSN_LSX(vpickve2gr_hu, rv_i)
INSN_LSX(vpickve2gr_wu, rv_i)
INSN_LSX(vpickve2gr_du, rv_i)

INSN_LSX(vreplgr2vr_b, vr)
INSN_LSX(vreplgr2vr_h, vr)
INSN_LSX(vreplgr2vr_w, vr)
INSN_LSX(vreplgr2vr_d, vr)
110 changes: 110 additions & 0 deletions target/loongarch/insn_trans/trans_lsx.c.inc
View file
Original file line number Diff line number Diff line change
Expand Up @@ -3823,3 +3823,113 @@ TRANS(vsetallnez_b, gen_cv, gen_helper_vsetallnez_b)
TRANS(vsetallnez_h, gen_cv, gen_helper_vsetallnez_h)
TRANS(vsetallnez_w, gen_cv, gen_helper_vsetallnez_w)
TRANS(vsetallnez_d, gen_cv, gen_helper_vsetallnez_d)

static bool trans_vinsgr2vr_b(DisasContext *ctx, arg_vr_i *a)
{
CHECK_SXE;
tcg_gen_st8_i64(cpu_gpr[a->rj], cpu_env,
offsetof(CPULoongArchState, fpr[a->vd].vreg.B(a->imm)));
return true;
}

static bool trans_vinsgr2vr_h(DisasContext *ctx, arg_vr_i *a)
{
CHECK_SXE;
tcg_gen_st16_i64(cpu_gpr[a->rj], cpu_env,
offsetof(CPULoongArchState, fpr[a->vd].vreg.H(a->imm)));
return true;
}

static bool trans_vinsgr2vr_w(DisasContext *ctx, arg_vr_i *a)
{
CHECK_SXE;
tcg_gen_st32_i64(cpu_gpr[a->rj], cpu_env,
offsetof(CPULoongArchState, fpr[a->vd].vreg.W(a->imm)));
return true;
}

static bool trans_vinsgr2vr_d(DisasContext *ctx, arg_vr_i *a)
{
CHECK_SXE;
tcg_gen_st_i64(cpu_gpr[a->rj], cpu_env,
offsetof(CPULoongArchState, fpr[a->vd].vreg.D(a->imm)));
return true;
}

static bool trans_vpickve2gr_b(DisasContext *ctx, arg_rv_i *a)
{
CHECK_SXE;
tcg_gen_ld8s_i64(cpu_gpr[a->rd], cpu_env,
offsetof(CPULoongArchState, fpr[a->vj].vreg.B(a->imm)));
return true;
}

static bool trans_vpickve2gr_h(DisasContext *ctx, arg_rv_i *a)
{
CHECK_SXE;
tcg_gen_ld16s_i64(cpu_gpr[a->rd], cpu_env,
offsetof(CPULoongArchState, fpr[a->vj].vreg.H(a->imm)));
return true;
}

static bool trans_vpickve2gr_w(DisasContext *ctx, arg_rv_i *a)
{
CHECK_SXE;
tcg_gen_ld32s_i64(cpu_gpr[a->rd], cpu_env,
offsetof(CPULoongArchState, fpr[a->vj].vreg.W(a->imm)));
return true;
}

static bool trans_vpickve2gr_d(DisasContext *ctx, arg_rv_i *a)
{
CHECK_SXE;
tcg_gen_ld_i64(cpu_gpr[a->rd], cpu_env,
offsetof(CPULoongArchState, fpr[a->vj].vreg.D(a->imm)));
return true;
}

static bool trans_vpickve2gr_bu(DisasContext *ctx, arg_rv_i *a)
{
CHECK_SXE;
tcg_gen_ld8u_i64(cpu_gpr[a->rd], cpu_env,
offsetof(CPULoongArchState, fpr[a->vj].vreg.B(a->imm)));
return true;
}

static bool trans_vpickve2gr_hu(DisasContext *ctx, arg_rv_i *a)
{
CHECK_SXE;
tcg_gen_ld16u_i64(cpu_gpr[a->rd], cpu_env,
offsetof(CPULoongArchState, fpr[a->vj].vreg.H(a->imm)));
return true;
}

static bool trans_vpickve2gr_wu(DisasContext *ctx, arg_rv_i *a)
{
CHECK_SXE;
tcg_gen_ld32u_i64(cpu_gpr[a->rd], cpu_env,
offsetof(CPULoongArchState, fpr[a->vj].vreg.W(a->imm)));
return true;
}

static bool trans_vpickve2gr_du(DisasContext *ctx, arg_rv_i *a)
{
CHECK_SXE;
tcg_gen_ld_i64(cpu_gpr[a->rd], cpu_env,
offsetof(CPULoongArchState, fpr[a->vj].vreg.D(a->imm)));
return true;
}

static bool gvec_dup(DisasContext *ctx, arg_vr *a, MemOp mop)
{
CHECK_SXE;

tcg_gen_gvec_dup_i64(mop, vec_full_offset(a->vd),
16, ctx->vl/8, cpu_gpr[a->rj]);
return true;
}

TRANS(vreplgr2vr_b, gvec_dup, MO_8)
TRANS(vreplgr2vr_h, gvec_dup, MO_16)
TRANS(vreplgr2vr_w, gvec_dup, MO_32)
TRANS(vreplgr2vr_d, gvec_dup, MO_64)
30 changes: 30 additions & 0 deletions target/loongarch/insns.decode
View file
Original file line number Diff line number Diff line change
Expand Up @@ -496,6 +496,9 @@ dbcl 0000 00000010 10101 ............... @i15
&vv_i vd vj imm
&vvvv vd vj vk va
&vvv_fcond vd vj vk fcond
&vr_i vd rj imm
&rv_i rd vj imm
&vr vd rj

#
# LSX Formats
Expand All @@ -512,6 +515,15 @@ dbcl 0000 00000010 10101 ............... @i15
@vv_i5 .... ........ ..... imm:s5 vj:5 vd:5 &vv_i
@vvvv .... ........ va:5 vk:5 vj:5 vd:5 &vvvv
@vvv_fcond .... ........ fcond:5 vk:5 vj:5 vd:5 &vvv_fcond
@vr_ui4 .... ........ ..... . imm:4 rj:5 vd:5 &vr_i
@vr_ui3 .... ........ ..... .. imm:3 rj:5 vd:5 &vr_i
@vr_ui2 .... ........ ..... ... imm:2 rj:5 vd:5 &vr_i
@vr_ui1 .... ........ ..... .... imm:1 rj:5 vd:5 &vr_i
@rv_ui4 .... ........ ..... . imm:4 vj:5 rd:5 &rv_i
@rv_ui3 .... ........ ..... .. imm:3 vj:5 rd:5 &rv_i
@rv_ui2 .... ........ ..... ... imm:2 vj:5 rd:5 &rv_i
@rv_ui1 .... ........ ..... .... imm:1 vj:5 rd:5 &rv_i
@vr .... ........ ..... ..... rj:5 vd:5 &vr

vadd_b 0111 00000000 10100 ..... ..... ..... @vvv
vadd_h 0111 00000000 10101 ..... ..... ..... @vvv
Expand Down Expand Up @@ -1167,3 +1179,21 @@ vsetallnez_b 0111 00101001 11001 01100 ..... 00 ... @cv
vsetallnez_h 0111 00101001 11001 01101 ..... 00 ... @cv
vsetallnez_w 0111 00101001 11001 01110 ..... 00 ... @cv
vsetallnez_d 0111 00101001 11001 01111 ..... 00 ... @cv

vinsgr2vr_b 0111 00101110 10111 0 .... ..... ..... @vr_ui4
vinsgr2vr_h 0111 00101110 10111 10 ... ..... ..... @vr_ui3
vinsgr2vr_w 0111 00101110 10111 110 .. ..... ..... @vr_ui2
vinsgr2vr_d 0111 00101110 10111 1110 . ..... ..... @vr_ui1
vpickve2gr_b 0111 00101110 11111 0 .... ..... ..... @rv_ui4
vpickve2gr_h 0111 00101110 11111 10 ... ..... ..... @rv_ui3
vpickve2gr_w 0111 00101110 11111 110 .. ..... ..... @rv_ui2
vpickve2gr_d 0111 00101110 11111 1110 . ..... ..... @rv_ui1
vpickve2gr_bu 0111 00101111 00111 0 .... ..... ..... @rv_ui4
vpickve2gr_hu 0111 00101111 00111 10 ... ..... ..... @rv_ui3
vpickve2gr_wu 0111 00101111 00111 110 .. ..... ..... @rv_ui2
vpickve2gr_du 0111 00101111 00111 1110 . ..... ..... @rv_ui1

vreplgr2vr_b 0111 00101001 11110 00000 ..... ..... @vr
vreplgr2vr_h 0111 00101001 11110 00001 ..... ..... @vr
vreplgr2vr_w 0111 00101001 11110 00010 ..... ..... @vr
vreplgr2vr_d 0111 00101001 11110 00011 ..... ..... @vr

0 comments on commit cdbdefb

Please sign in to comment.