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tcg/i386: Implement bitsel for avx512
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The general ternary logic operation can implement BITSEL.
Funnel the 4-operand operation into three variants of the
3-operand instruction, depending on input operand overlap.

Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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rth7680 committed Mar 4, 2022
1 parent 3143767 commit cf32076
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Showing 2 changed files with 20 additions and 2 deletions.
20 changes: 19 additions & 1 deletion tcg/i386/tcg-target.c.inc
Expand Up @@ -2898,7 +2898,7 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,

TCGType type = vecl + TCG_TYPE_V64;
int insn, sub;
TCGArg a0, a1, a2;
TCGArg a0, a1, a2, a3;

a0 = args[0];
a1 = args[1];
Expand Down Expand Up @@ -3122,6 +3122,22 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
sub = 0xdd; /* orB!C */
goto gen_simd_imm8;

case INDEX_op_bitsel_vec:
insn = OPC_VPTERNLOGQ;
a3 = args[3];
if (a0 == a1) {
a1 = a2;
a2 = a3;
sub = 0xca; /* A?B:C */
} else if (a0 == a2) {
a2 = a3;
sub = 0xe2; /* B?A:C */
} else {
tcg_out_mov(s, type, a0, a3);
sub = 0xb8; /* B?C:A */
}
goto gen_simd_imm8;

gen_simd_imm8:
tcg_debug_assert(insn != OPC_UD2);
if (type == TCG_TYPE_V256) {
Expand Down Expand Up @@ -3390,6 +3406,7 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
case INDEX_op_x86_vpshrdv_vec:
return C_O1_I3(x, 0, x, x);

case INDEX_op_bitsel_vec:
case INDEX_op_x86_vpblendvb_vec:
return C_O1_I3(x, x, x, x);

Expand All @@ -3412,6 +3429,7 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
case INDEX_op_nor_vec:
case INDEX_op_eqv_vec:
case INDEX_op_not_vec:
case INDEX_op_bitsel_vec:
return 1;
case INDEX_op_cmp_vec:
case INDEX_op_cmpsel_vec:
Expand Down
2 changes: 1 addition & 1 deletion tcg/i386/tcg-target.h
Expand Up @@ -204,7 +204,7 @@ extern bool have_movbe;
#define TCG_TARGET_HAS_mul_vec 1
#define TCG_TARGET_HAS_sat_vec 1
#define TCG_TARGET_HAS_minmax_vec 1
#define TCG_TARGET_HAS_bitsel_vec 0
#define TCG_TARGET_HAS_bitsel_vec have_avx512vl
#define TCG_TARGET_HAS_cmpsel_vec -1

#define TCG_TARGET_deposit_i32_valid(ofs, len) \
Expand Down

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