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tests/qtest: Add test for Aspeed HACE accumulative mode
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This add two addition test cases for accumulative mode under sg enabled.

The input vector was manually craft with "abc" + bit 1 + padding zeros + L.
The padding length depends on algorithm, i.e. SHA512 (1024 bit),
SHA256 (512 bit).

The result was calculated by command line sha512sum/sha256sum utilities
without padding, i.e. only "abc" ascii text.

Signed-off-by: Troy Lee <troy_lee@aspeedtech.com>
Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
Acked-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
[ clg: checkpatch fixes ]
Message-Id: <20220426021120.28255-4-steven_lee@aspeedtech.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
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@stevenlee7189 @legoater
stevenlee7189 authored and legoater committed May 2, 2022
1 parent 5cd7d85 commit e0c371a
Showing 1 changed file with 147 additions and 0 deletions.
147 changes: 147 additions & 0 deletions tests/qtest/aspeed_hace-test.c
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Expand Up @@ -20,6 +20,7 @@
#define HACE_ALGO_SHA512 (BIT(5) | BIT(6))
#define HACE_ALGO_SHA384 (BIT(5) | BIT(6) | BIT(10))
#define HACE_SG_EN BIT(18)
#define HACE_ACCUM_EN BIT(8)

#define HACE_STS 0x1c
#define HACE_RSA_ISR BIT(13)
Expand Down Expand Up @@ -95,6 +96,57 @@ static const uint8_t test_result_sg_sha256[] = {
0x55, 0x1e, 0x1e, 0xc5, 0x80, 0xdd, 0x6d, 0x5a, 0x6e, 0xcd, 0xe9, 0xf3,
0xd3, 0x5e, 0x6e, 0x4a, 0x71, 0x7f, 0xbd, 0xe4};

/*
* The accumulative mode requires firmware to provide internal initial state
* and message padding (including length L at the end of padding).
*
* This test vector is a ascii text "abc" with padding message.
*
* Expected results were generated using command line utitiles:
*
* echo -n -e 'abc' | dd of=/tmp/test
* for hash in sha512sum sha256sum; do $hash /tmp/test; done
*/
static const uint8_t test_vector_accum_512[] = {
0x61, 0x62, 0x63, 0x80, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18};

static const uint8_t test_vector_accum_256[] = {
0x61, 0x62, 0x63, 0x80, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18};

static const uint8_t test_result_accum_sha512[] = {
0xdd, 0xaf, 0x35, 0xa1, 0x93, 0x61, 0x7a, 0xba, 0xcc, 0x41, 0x73, 0x49,
0xae, 0x20, 0x41, 0x31, 0x12, 0xe6, 0xfa, 0x4e, 0x89, 0xa9, 0x7e, 0xa2,
0x0a, 0x9e, 0xee, 0xe6, 0x4b, 0x55, 0xd3, 0x9a, 0x21, 0x92, 0x99, 0x2a,
0x27, 0x4f, 0xc1, 0xa8, 0x36, 0xba, 0x3c, 0x23, 0xa3, 0xfe, 0xeb, 0xbd,
0x45, 0x4d, 0x44, 0x23, 0x64, 0x3c, 0xe8, 0x0e, 0x2a, 0x9a, 0xc9, 0x4f,
0xa5, 0x4c, 0xa4, 0x9f};

static const uint8_t test_result_accum_sha256[] = {
0xba, 0x78, 0x16, 0xbf, 0x8f, 0x01, 0xcf, 0xea, 0x41, 0x41, 0x40, 0xde,
0x5d, 0xae, 0x22, 0x23, 0xb0, 0x03, 0x61, 0xa3, 0x96, 0x17, 0x7a, 0x9c,
0xb4, 0x10, 0xff, 0x61, 0xf2, 0x00, 0x15, 0xad};

static void write_regs(QTestState *s, uint32_t base, uint32_t src,
uint32_t length, uint32_t out, uint32_t method)
Expand Down Expand Up @@ -307,6 +359,88 @@ static void test_sha512_sg(const char *machine, const uint32_t base,
qtest_quit(s);
}

static void test_sha256_accum(const char *machine, const uint32_t base,
const uint32_t src_addr)
{
QTestState *s = qtest_init(machine);

const uint32_t buffer_addr = src_addr + 0x1000000;
const uint32_t digest_addr = src_addr + 0x4000000;
uint8_t digest[32] = {0};
struct AspeedSgList array[] = {
{ cpu_to_le32(sizeof(test_vector_accum_256) | SG_LIST_LEN_LAST),
cpu_to_le32(buffer_addr) },
};

/* Check engine is idle, no busy or irq bits set */
g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0);

/* Write test vector into memory */
qtest_memwrite(s, buffer_addr, test_vector_accum_256,
sizeof(test_vector_accum_256));
qtest_memwrite(s, src_addr, array, sizeof(array));

write_regs(s, base, src_addr, sizeof(test_vector_accum_256),
digest_addr, HACE_ALGO_SHA256 | HACE_SG_EN | HACE_ACCUM_EN);

/* Check hash IRQ status is asserted */
g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0x00000200);

/* Clear IRQ status and check status is deasserted */
qtest_writel(s, base + HACE_STS, 0x00000200);
g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0);

/* Read computed digest from memory */
qtest_memread(s, digest_addr, digest, sizeof(digest));

/* Check result of computation */
g_assert_cmpmem(digest, sizeof(digest),
test_result_accum_sha256, sizeof(digest));

qtest_quit(s);
}

static void test_sha512_accum(const char *machine, const uint32_t base,
const uint32_t src_addr)
{
QTestState *s = qtest_init(machine);

const uint32_t buffer_addr = src_addr + 0x1000000;
const uint32_t digest_addr = src_addr + 0x4000000;
uint8_t digest[64] = {0};
struct AspeedSgList array[] = {
{ cpu_to_le32(sizeof(test_vector_accum_512) | SG_LIST_LEN_LAST),
cpu_to_le32(buffer_addr) },
};

/* Check engine is idle, no busy or irq bits set */
g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0);

/* Write test vector into memory */
qtest_memwrite(s, buffer_addr, test_vector_accum_512,
sizeof(test_vector_accum_512));
qtest_memwrite(s, src_addr, array, sizeof(array));

write_regs(s, base, src_addr, sizeof(test_vector_accum_512),
digest_addr, HACE_ALGO_SHA512 | HACE_SG_EN | HACE_ACCUM_EN);

/* Check hash IRQ status is asserted */
g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0x00000200);

/* Clear IRQ status and check status is deasserted */
qtest_writel(s, base + HACE_STS, 0x00000200);
g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0);

/* Read computed digest from memory */
qtest_memread(s, digest_addr, digest, sizeof(digest));

/* Check result of computation */
g_assert_cmpmem(digest, sizeof(digest),
test_result_accum_sha512, sizeof(digest));

qtest_quit(s);
}

struct masks {
uint32_t src;
uint32_t dest;
Expand Down Expand Up @@ -395,6 +529,16 @@ static void test_sha512_sg_ast2600(void)
test_sha512_sg("-machine ast2600-evb", 0x1e6d0000, 0x80000000);
}

static void test_sha256_accum_ast2600(void)
{
test_sha256_accum("-machine ast2600-evb", 0x1e6d0000, 0x80000000);
}

static void test_sha512_accum_ast2600(void)
{
test_sha512_accum("-machine ast2600-evb", 0x1e6d0000, 0x80000000);
}

static void test_addresses_ast2600(void)
{
test_addresses("-machine ast2600-evb", 0x1e6d0000, &ast2600_masks);
Expand Down Expand Up @@ -454,6 +598,9 @@ int main(int argc, char **argv)
qtest_add_func("ast2600/hace/sha512_sg", test_sha512_sg_ast2600);
qtest_add_func("ast2600/hace/sha256_sg", test_sha256_sg_ast2600);

qtest_add_func("ast2600/hace/sha512_accum", test_sha512_accum_ast2600);
qtest_add_func("ast2600/hace/sha256_accum", test_sha256_accum_ast2600);

qtest_add_func("ast2500/hace/addresses", test_addresses_ast2500);
qtest_add_func("ast2500/hace/sha512", test_sha512_ast2500);
qtest_add_func("ast2500/hace/sha256", test_sha256_ast2500);
Expand Down

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