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Merge tag 'pull-riscv-to-apply-20220907' of https://github.com/alista…
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…ir23/qemu into staging

First RISC-V PR for QEMU 7.2

* Update [m|h]tinst CSR in interrupt handling
* Force disable extensions if priv spec version does not match
* fix shifts shamt value for rv128c
* move zmmul out of the experimental
* virt: pass random seed to fdt
* Add checks for supported extension combinations
* Upgrade OpenSBI to v1.1
* Fix typo and restore Pointer Masking functionality for RISC-V
* Add mask agnostic behaviour (rvv_ma_all_1s) for vector extension
* Add Zihintpause support
* opentitan: bump opentitan version
* microchip_pfsoc: fix kernel panics due to missing peripherals
* Remove additional priv version check for mcountinhibit
* virt machine device tree improvements
* Add xicondops in ISA entry
* Use official extension names for AIA CSRs

# -----BEGIN PGP SIGNATURE-----
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# =7mGD
# -----END PGP SIGNATURE-----
# gpg: Signature made Wed 07 Sep 2022 04:02:45 EDT
# gpg:                using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: F6C4 AC46 D493 4868 D3B8  CE8F 21E1 0D29 DF97 7054

* tag 'pull-riscv-to-apply-20220907' of https://github.com/alistair23/qemu: (44 commits)
  target/riscv: Update the privilege field for sscofpmf CSRs
  hw/riscv: virt: Add PMU DT node to the device tree
  target/riscv: Add few cache related PMU events
  target/riscv: Simplify counter predicate function
  target/riscv: Add sscofpmf extension support
  target/riscv: Add vstimecmp support
  target/riscv: Add stimecmp support
  hw/intc: Move mtimer/mtimecmp to aclint
  target/riscv: Use official extension names for AIA CSRs
  target/riscv: Add xicondops in ISA entry
  hw/core: fix platform bus node name
  hw/riscv: virt: fix syscon subnode paths
  hw/riscv: virt: fix the plic's address cells
  hw/riscv: virt: fix uart node name
  target/riscv: Remove additional priv version check for mcountinhibit
  hw/riscv: microchip_pfsoc: fix kernel panics due to missing peripherals
  hw/riscv: opentitan: bump opentitan version
  target/riscv: Fix priority of csr related check in riscv_csrrw_check
  hw/riscv: remove 'fdt' param from riscv_setup_rom_reset_vec()
  target/riscv: Add Zihintpause support
  ...

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
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@stefanhaRH
stefanhaRH committed Sep 7, 2022
2 parents 946e9bc + f055156 commit e46e262
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Showing 40 changed files with 2,229 additions and 559 deletions.
27 changes: 21 additions & 6 deletions disas/riscv.c
View file
Expand Up @@ -2402,10 +2402,25 @@ static int32_t operand_sbimm12(rv_inst inst)
((inst << 56) >> 63) << 11;
}

static uint32_t operand_cimmsh6(rv_inst inst)
static uint32_t operand_cimmshl6(rv_inst inst, rv_isa isa)
{
return ((inst << 51) >> 63) << 5 |
int imm = ((inst << 51) >> 63) << 5 |
(inst << 57) >> 59;
if (isa == rv128) {
imm = imm ? imm : 64;
}
return imm;
}

static uint32_t operand_cimmshr6(rv_inst inst, rv_isa isa)
{
int imm = ((inst << 51) >> 63) << 5 |
(inst << 57) >> 59;
if (isa == rv128) {
imm = imm | (imm & 32) << 1;
imm = imm ? imm : 64;
}
return imm;
}

static int32_t operand_cimmi(rv_inst inst)
Expand Down Expand Up @@ -2529,7 +2544,7 @@ static uint32_t operand_rnum(rv_inst inst)

/* decode operands */

static void decode_inst_operands(rv_decode *dec)
static void decode_inst_operands(rv_decode *dec, rv_isa isa)
{
rv_inst inst = dec->inst;
dec->codec = opcode_data[dec->op].codec;
Expand Down Expand Up @@ -2652,7 +2667,7 @@ static void decode_inst_operands(rv_decode *dec)
case rv_codec_cb_sh6:
dec->rd = dec->rs1 = operand_crs1rdq(inst) + 8;
dec->rs2 = rv_ireg_zero;
dec->imm = operand_cimmsh6(inst);
dec->imm = operand_cimmshr6(inst, isa);
break;
case rv_codec_ci:
dec->rd = dec->rs1 = operand_crs1rd(inst);
Expand All @@ -2667,7 +2682,7 @@ static void decode_inst_operands(rv_decode *dec)
case rv_codec_ci_sh6:
dec->rd = dec->rs1 = operand_crs1rd(inst);
dec->rs2 = rv_ireg_zero;
dec->imm = operand_cimmsh6(inst);
dec->imm = operand_cimmshl6(inst, isa);
break;
case rv_codec_ci_16sp:
dec->rd = rv_ireg_sp;
Expand Down Expand Up @@ -3193,7 +3208,7 @@ disasm_inst(char *buf, size_t buflen, rv_isa isa, uint64_t pc, rv_inst inst)
dec.pc = pc;
dec.inst = inst;
decode_inst_opcode(&dec, isa);
decode_inst_operands(&dec);
decode_inst_operands(&dec, isa);
decode_inst_decompress(&dec, isa);
decode_inst_lift_pseudo(&dec);
format_inst(buf, buflen, 16, &dec);
Expand Down
2 changes: 1 addition & 1 deletion docs/about/build-platforms.rst
View file
Expand Up @@ -46,7 +46,7 @@ Those hosts are officially supported, with various accelerators:
* - PPC
- kvm, tcg
* - RISC-V
- tcg
- kvm, tcg
* - s390x
- kvm, tcg
* - SPARC
Expand Down
2 changes: 1 addition & 1 deletion hw/core/sysbus-fdt.c
View file
Expand Up @@ -539,7 +539,7 @@ void platform_bus_add_all_fdt_nodes(void *fdt, const char *intc, hwaddr addr,

assert(fdt);

node = g_strdup_printf("/platform@%"PRIx64, addr);
node = g_strdup_printf("/platform-bus@%"PRIx64, addr);

/* Create a /platform node that we can put all devices into */
qemu_fdt_add_subnode(fdt, node);
Expand Down
48 changes: 34 additions & 14 deletions hw/intc/riscv_aclint.c
View file
Expand Up @@ -32,6 +32,7 @@
#include "hw/intc/riscv_aclint.h"
#include "qemu/timer.h"
#include "hw/irq.h"
#include "migration/vmstate.h"

typedef struct riscv_aclint_mtimer_callback {
RISCVAclintMTimerState *s;
Expand Down Expand Up @@ -65,19 +66,22 @@ static void riscv_aclint_mtimer_write_timecmp(RISCVAclintMTimerState *mtimer,

uint64_t rtc_r = cpu_riscv_read_rtc(mtimer);

cpu->env.timecmp = value;
if (cpu->env.timecmp <= rtc_r) {
/* Compute the relative hartid w.r.t the socket */
hartid = hartid - mtimer->hartid_base;

mtimer->timecmp[hartid] = value;
if (mtimer->timecmp[hartid] <= rtc_r) {
/*
* If we're setting an MTIMECMP value in the "past",
* immediately raise the timer interrupt
*/
qemu_irq_raise(mtimer->timer_irqs[hartid - mtimer->hartid_base]);
qemu_irq_raise(mtimer->timer_irqs[hartid]);
return;
}

/* otherwise, set up the future timer interrupt */
qemu_irq_lower(mtimer->timer_irqs[hartid - mtimer->hartid_base]);
diff = cpu->env.timecmp - rtc_r;
qemu_irq_lower(mtimer->timer_irqs[hartid]);
diff = mtimer->timecmp[hartid] - rtc_r;
/* back to ns (note args switched in muldiv64) */
uint64_t ns_diff = muldiv64(diff, NANOSECONDS_PER_SECOND, timebase_freq);

Expand All @@ -102,7 +106,7 @@ static void riscv_aclint_mtimer_write_timecmp(RISCVAclintMTimerState *mtimer,
next = MIN(next, INT64_MAX);
}

timer_mod(cpu->env.timer, next);
timer_mod(mtimer->timers[hartid], next);
}

/*
Expand Down Expand Up @@ -133,11 +137,11 @@ static uint64_t riscv_aclint_mtimer_read(void *opaque, hwaddr addr,
"aclint-mtimer: invalid hartid: %zu", hartid);
} else if ((addr & 0x7) == 0) {
/* timecmp_lo for RV32/RV64 or timecmp for RV64 */
uint64_t timecmp = env->timecmp;
uint64_t timecmp = mtimer->timecmp[hartid];
return (size == 4) ? (timecmp & 0xFFFFFFFF) : timecmp;
} else if ((addr & 0x7) == 4) {
/* timecmp_hi */
uint64_t timecmp = env->timecmp;
uint64_t timecmp = mtimer->timecmp[hartid];
return (timecmp >> 32) & 0xFFFFFFFF;
} else {
qemu_log_mask(LOG_UNIMP,
Expand Down Expand Up @@ -177,7 +181,7 @@ static void riscv_aclint_mtimer_write(void *opaque, hwaddr addr,
} else if ((addr & 0x7) == 0) {
if (size == 4) {
/* timecmp_lo for RV32/RV64 */
uint64_t timecmp_hi = env->timecmp >> 32;
uint64_t timecmp_hi = mtimer->timecmp[hartid] >> 32;
riscv_aclint_mtimer_write_timecmp(mtimer, RISCV_CPU(cpu), hartid,
timecmp_hi << 32 | (value & 0xFFFFFFFF));
} else {
Expand All @@ -188,7 +192,7 @@ static void riscv_aclint_mtimer_write(void *opaque, hwaddr addr,
} else if ((addr & 0x7) == 4) {
if (size == 4) {
/* timecmp_hi for RV32/RV64 */
uint64_t timecmp_lo = env->timecmp;
uint64_t timecmp_lo = mtimer->timecmp[hartid];
riscv_aclint_mtimer_write_timecmp(mtimer, RISCV_CPU(cpu), hartid,
value << 32 | (timecmp_lo & 0xFFFFFFFF));
} else {
Expand Down Expand Up @@ -234,7 +238,7 @@ static void riscv_aclint_mtimer_write(void *opaque, hwaddr addr,
}
riscv_aclint_mtimer_write_timecmp(mtimer, RISCV_CPU(cpu),
mtimer->hartid_base + i,
env->timecmp);
mtimer->timecmp[i]);
}
return;
}
Expand Down Expand Up @@ -284,6 +288,8 @@ static void riscv_aclint_mtimer_realize(DeviceState *dev, Error **errp)
s->timer_irqs = g_new(qemu_irq, s->num_harts);
qdev_init_gpio_out(dev, s->timer_irqs, s->num_harts);

s->timers = g_new0(QEMUTimer *, s->num_harts);
s->timecmp = g_new0(uint64_t, s->num_harts);
/* Claim timer interrupt bits */
for (i = 0; i < s->num_harts; i++) {
RISCVCPU *cpu = RISCV_CPU(qemu_get_cpu(s->hartid_base + i));
Expand All @@ -310,13 +316,26 @@ static void riscv_aclint_mtimer_reset_enter(Object *obj, ResetType type)
riscv_aclint_mtimer_write(mtimer, mtimer->time_base, 0, 8);
}

static const VMStateDescription vmstate_riscv_mtimer = {
.name = "riscv_mtimer",
.version_id = 1,
.minimum_version_id = 1,
.fields = (VMStateField[]) {
VMSTATE_VARRAY_UINT32(timecmp, RISCVAclintMTimerState,
num_harts, 0,
vmstate_info_uint64, uint64_t),
VMSTATE_END_OF_LIST()
}
};

static void riscv_aclint_mtimer_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->realize = riscv_aclint_mtimer_realize;
device_class_set_props(dc, riscv_aclint_mtimer_properties);
ResettableClass *rc = RESETTABLE_CLASS(klass);
rc->phases.enter = riscv_aclint_mtimer_reset_enter;
dc->vmsd = &vmstate_riscv_mtimer;
}

static const TypeInfo riscv_aclint_mtimer_info = {
Expand All @@ -336,6 +355,7 @@ DeviceState *riscv_aclint_mtimer_create(hwaddr addr, hwaddr size,
{
int i;
DeviceState *dev = qdev_new(TYPE_RISCV_ACLINT_MTIMER);
RISCVAclintMTimerState *s = RISCV_ACLINT_MTIMER(dev);

assert(num_harts <= RISCV_ACLINT_MAX_HARTS);
assert(!(addr & 0x7));
Expand Down Expand Up @@ -366,11 +386,11 @@ DeviceState *riscv_aclint_mtimer_create(hwaddr addr, hwaddr size,
riscv_cpu_set_rdtime_fn(env, cpu_riscv_read_rtc, dev);
}

cb->s = RISCV_ACLINT_MTIMER(dev);
cb->s = s;
cb->num = i;
env->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
s->timers[i] = timer_new_ns(QEMU_CLOCK_VIRTUAL,
&riscv_aclint_mtimer_cb, cb);
env->timecmp = 0;
s->timecmp[i] = 0;

qdev_connect_gpio_out(dev, i,
qdev_get_gpio_in(DEVICE(rvcpu), IRQ_M_TIMER));
Expand Down
4 changes: 3 additions & 1 deletion hw/intc/riscv_imsic.c
View file
Expand Up @@ -344,9 +344,11 @@ static void riscv_imsic_realize(DeviceState *dev, Error **errp)

/* Force select AIA feature and setup CSR read-modify-write callback */
if (env) {
riscv_set_feature(env, RISCV_FEATURE_AIA);
if (!imsic->mmode) {
rcpu->cfg.ext_ssaia = true;
riscv_cpu_set_geilen(env, imsic->num_pages - 1);
} else {
rcpu->cfg.ext_smaia = true;
}
riscv_cpu_set_aia_ireg_rmw_fn(env, (imsic->mmode) ? PRV_M : PRV_S,
riscv_imsic_rmw, imsic);
Expand Down
4 changes: 1 addition & 3 deletions hw/riscv/boot.c
View file
Expand Up @@ -286,7 +286,7 @@ void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts
hwaddr start_addr,
hwaddr rom_base, hwaddr rom_size,
uint64_t kernel_entry,
uint64_t fdt_load_addr, void *fdt)
uint64_t fdt_load_addr)
{
int i;
uint32_t start_addr_hi32 = 0x00000000;
Expand Down Expand Up @@ -326,8 +326,6 @@ void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts
rom_base, &address_space_memory);
riscv_rom_copy_firmware_info(machine, rom_base, rom_size, sizeof(reset_vec),
kernel_entry);

return;
}

void riscv_setup_direct_kernel(hwaddr kernel_addr, hwaddr fdt_addr)
Expand Down
69 changes: 62 additions & 7 deletions hw/riscv/microchip_pfsoc.c
View file
Expand Up @@ -100,28 +100,40 @@ static const MemMapEntry microchip_pfsoc_memmap[] = {
[MICROCHIP_PFSOC_L2LIM] = { 0x8000000, 0x2000000 },
[MICROCHIP_PFSOC_PLIC] = { 0xc000000, 0x4000000 },
[MICROCHIP_PFSOC_MMUART0] = { 0x20000000, 0x1000 },
[MICROCHIP_PFSOC_WDOG0] = { 0x20001000, 0x1000 },
[MICROCHIP_PFSOC_SYSREG] = { 0x20002000, 0x2000 },
[MICROCHIP_PFSOC_AXISW] = { 0x20004000, 0x1000 },
[MICROCHIP_PFSOC_MPUCFG] = { 0x20005000, 0x1000 },
[MICROCHIP_PFSOC_FMETER] = { 0x20006000, 0x1000 },
[MICROCHIP_PFSOC_DDR_SGMII_PHY] = { 0x20007000, 0x1000 },
[MICROCHIP_PFSOC_EMMC_SD] = { 0x20008000, 0x1000 },
[MICROCHIP_PFSOC_DDR_CFG] = { 0x20080000, 0x40000 },
[MICROCHIP_PFSOC_MMUART1] = { 0x20100000, 0x1000 },
[MICROCHIP_PFSOC_MMUART2] = { 0x20102000, 0x1000 },
[MICROCHIP_PFSOC_MMUART3] = { 0x20104000, 0x1000 },
[MICROCHIP_PFSOC_MMUART4] = { 0x20106000, 0x1000 },
[MICROCHIP_PFSOC_WDOG1] = { 0x20101000, 0x1000 },
[MICROCHIP_PFSOC_WDOG2] = { 0x20103000, 0x1000 },
[MICROCHIP_PFSOC_WDOG3] = { 0x20105000, 0x1000 },
[MICROCHIP_PFSOC_WDOG4] = { 0x20106000, 0x1000 },
[MICROCHIP_PFSOC_SPI0] = { 0x20108000, 0x1000 },
[MICROCHIP_PFSOC_SPI1] = { 0x20109000, 0x1000 },
[MICROCHIP_PFSOC_I2C0] = { 0x2010a000, 0x1000 },
[MICROCHIP_PFSOC_I2C1] = { 0x2010b000, 0x1000 },
[MICROCHIP_PFSOC_CAN0] = { 0x2010c000, 0x1000 },
[MICROCHIP_PFSOC_CAN1] = { 0x2010d000, 0x1000 },
[MICROCHIP_PFSOC_GEM0] = { 0x20110000, 0x2000 },
[MICROCHIP_PFSOC_GEM1] = { 0x20112000, 0x2000 },
[MICROCHIP_PFSOC_GPIO0] = { 0x20120000, 0x1000 },
[MICROCHIP_PFSOC_GPIO1] = { 0x20121000, 0x1000 },
[MICROCHIP_PFSOC_GPIO2] = { 0x20122000, 0x1000 },
[MICROCHIP_PFSOC_RTC] = { 0x20124000, 0x1000 },
[MICROCHIP_PFSOC_ENVM_CFG] = { 0x20200000, 0x1000 },
[MICROCHIP_PFSOC_ENVM_DATA] = { 0x20220000, 0x20000 },
[MICROCHIP_PFSOC_USB] = { 0x20201000, 0x1000 },
[MICROCHIP_PFSOC_QSPI_XIP] = { 0x21000000, 0x1000000 },
[MICROCHIP_PFSOC_IOSCB] = { 0x30000000, 0x10000000 },
[MICROCHIP_PFSOC_EMMC_SD_MUX] = { 0x4f000000, 0x4 },
[MICROCHIP_PFSOC_FABRIC_FIC3] = { 0x40000000, 0x20000000 },
[MICROCHIP_PFSOC_DRAM_LO] = { 0x80000000, 0x40000000 },
[MICROCHIP_PFSOC_DRAM_LO_ALIAS] = { 0xc0000000, 0x40000000 },
[MICROCHIP_PFSOC_DRAM_HI] = { 0x1000000000, 0x0 },
Expand Down Expand Up @@ -292,11 +304,21 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
sysbus_mmio_map(SYS_BUS_DEVICE(&s->sysreg), 0,
memmap[MICROCHIP_PFSOC_SYSREG].base);

/* AXISW */
create_unimplemented_device("microchip.pfsoc.axisw",
memmap[MICROCHIP_PFSOC_AXISW].base,
memmap[MICROCHIP_PFSOC_AXISW].size);

/* MPUCFG */
create_unimplemented_device("microchip.pfsoc.mpucfg",
memmap[MICROCHIP_PFSOC_MPUCFG].base,
memmap[MICROCHIP_PFSOC_MPUCFG].size);

/* FMETER */
create_unimplemented_device("microchip.pfsoc.fmeter",
memmap[MICROCHIP_PFSOC_FMETER].base,
memmap[MICROCHIP_PFSOC_FMETER].size);

/* DDR SGMII PHY */
sysbus_realize(SYS_BUS_DEVICE(&s->ddr_sgmii_phy), errp);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->ddr_sgmii_phy), 0,
Expand Down Expand Up @@ -336,6 +358,23 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART4_IRQ),
serial_hd(4));

/* Watchdogs */
create_unimplemented_device("microchip.pfsoc.watchdog0",
memmap[MICROCHIP_PFSOC_WDOG0].base,
memmap[MICROCHIP_PFSOC_WDOG0].size);
create_unimplemented_device("microchip.pfsoc.watchdog1",
memmap[MICROCHIP_PFSOC_WDOG1].base,
memmap[MICROCHIP_PFSOC_WDOG1].size);
create_unimplemented_device("microchip.pfsoc.watchdog2",
memmap[MICROCHIP_PFSOC_WDOG2].base,
memmap[MICROCHIP_PFSOC_WDOG2].size);
create_unimplemented_device("microchip.pfsoc.watchdog3",
memmap[MICROCHIP_PFSOC_WDOG3].base,
memmap[MICROCHIP_PFSOC_WDOG3].size);
create_unimplemented_device("microchip.pfsoc.watchdog4",
memmap[MICROCHIP_PFSOC_WDOG4].base,
memmap[MICROCHIP_PFSOC_WDOG4].size);

/* SPI */
create_unimplemented_device("microchip.pfsoc.spi0",
memmap[MICROCHIP_PFSOC_SPI0].base,
Expand All @@ -344,11 +383,27 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
memmap[MICROCHIP_PFSOC_SPI1].base,
memmap[MICROCHIP_PFSOC_SPI1].size);

/* I2C1 */
/* I2C */
create_unimplemented_device("microchip.pfsoc.i2c0",
memmap[MICROCHIP_PFSOC_I2C0].base,
memmap[MICROCHIP_PFSOC_I2C0].size);
create_unimplemented_device("microchip.pfsoc.i2c1",
memmap[MICROCHIP_PFSOC_I2C1].base,
memmap[MICROCHIP_PFSOC_I2C1].size);

/* CAN */
create_unimplemented_device("microchip.pfsoc.can0",
memmap[MICROCHIP_PFSOC_CAN0].base,
memmap[MICROCHIP_PFSOC_CAN0].size);
create_unimplemented_device("microchip.pfsoc.can1",
memmap[MICROCHIP_PFSOC_CAN1].base,
memmap[MICROCHIP_PFSOC_CAN1].size);

/* USB */
create_unimplemented_device("microchip.pfsoc.usb",
memmap[MICROCHIP_PFSOC_USB].base,
memmap[MICROCHIP_PFSOC_USB].size);

/* GEMs */

nd = &nd_table[0];
Expand Down Expand Up @@ -402,10 +457,10 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
sysbus_mmio_map(SYS_BUS_DEVICE(&s->ioscb), 0,
memmap[MICROCHIP_PFSOC_IOSCB].base);

/* eMMC/SD mux */
create_unimplemented_device("microchip.pfsoc.emmc_sd_mux",
memmap[MICROCHIP_PFSOC_EMMC_SD_MUX].base,
memmap[MICROCHIP_PFSOC_EMMC_SD_MUX].size);
/* FPGA Fabric */
create_unimplemented_device("microchip.pfsoc.fabricfic3",
memmap[MICROCHIP_PFSOC_FABRIC_FIC3].base,
memmap[MICROCHIP_PFSOC_FABRIC_FIC3].size);

/* QSPI Flash */
memory_region_init_rom(qspi_xip_mem, OBJECT(dev),
Expand Down Expand Up @@ -583,7 +638,7 @@ static void microchip_icicle_kit_machine_init(MachineState *machine)
riscv_setup_rom_reset_vec(machine, &s->soc.u_cpus, firmware_load_addr,
memmap[MICROCHIP_PFSOC_ENVM_DATA].base,
memmap[MICROCHIP_PFSOC_ENVM_DATA].size,
kernel_entry, fdt_load_addr, machine->fdt);
kernel_entry, fdt_load_addr);
}
}

Expand Down

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