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target/mips/translate: Add declarations for generic code
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Some CPU translation functions / registers / macros and
definitions can be used by ISA / ASE / extensions out of
the big translate.c file. Declare them in "translate.h".

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201207235539.4070364-3-f4bug@amsat.org>
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@philmd
philmd committed Jan 7, 2021
1 parent 33ef6aa commit e549850
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Showing 2 changed files with 49 additions and 34 deletions.
45 changes: 11 additions & 34 deletions target/mips/translate.c
View file
Expand Up @@ -38,11 +38,6 @@
#include "fpu_helper.h"
#include "translate.h"

#define MIPS_DEBUG_DISAS 0

/* MIPS major opcodes */
#define MASK_OP_MAJOR(op) (op & (0x3F << 26))

enum {
/* indirect opcode tables */
OPC_SPECIAL = (0x00 << 26),
Expand Down Expand Up @@ -2491,9 +2486,10 @@ enum {
};

/* global register indices */
static TCGv cpu_gpr[32], cpu_PC;
TCGv cpu_gpr[32], cpu_PC;
static TCGv cpu_HI[MIPS_DSP_ACC], cpu_LO[MIPS_DSP_ACC];
static TCGv cpu_dspctrl, btarget, bcond;
static TCGv cpu_dspctrl, btarget;
TCGv bcond;
static TCGv cpu_lladdr, cpu_llval;
static TCGv_i32 hflags;
static TCGv_i32 fpu_fcr0, fpu_fcr31;
Expand Down Expand Up @@ -2606,26 +2602,8 @@ static const char * const mxuregnames[] = {
};
#endif

#define LOG_DISAS(...) \
do { \
if (MIPS_DEBUG_DISAS) { \
qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__); \
} \
} while (0)

#define MIPS_INVAL(op) \
do { \
if (MIPS_DEBUG_DISAS) { \
qemu_log_mask(CPU_LOG_TB_IN_ASM, \
TARGET_FMT_lx ": %08x Invalid %s %03x %03x %03x\n", \
ctx->base.pc_next, ctx->opcode, op, \
ctx->opcode >> 26, ctx->opcode & 0x3F, \
((ctx->opcode >> 16) & 0x1F)); \
} \
} while (0)

/* General purpose registers moves. */
static inline void gen_load_gpr(TCGv t, int reg)
void gen_load_gpr(TCGv t, int reg)
{
if (reg == 0) {
tcg_gen_movi_tl(t, 0);
Expand All @@ -2634,7 +2612,7 @@ static inline void gen_load_gpr(TCGv t, int reg)
}
}

static inline void gen_store_gpr(TCGv t, int reg)
void gen_store_gpr(TCGv t, int reg)
{
if (reg != 0) {
tcg_gen_mov_tl(cpu_gpr[reg], t);
Expand Down Expand Up @@ -2763,7 +2741,7 @@ static inline void restore_cpu_state(CPUMIPSState *env, DisasContext *ctx)
}
}

static inline void generate_exception_err(DisasContext *ctx, int excp, int err)
void generate_exception_err(DisasContext *ctx, int excp, int err)
{
TCGv_i32 texcp = tcg_const_i32(excp);
TCGv_i32 terr = tcg_const_i32(err);
Expand All @@ -2774,12 +2752,12 @@ static inline void generate_exception_err(DisasContext *ctx, int excp, int err)
ctx->base.is_jmp = DISAS_NORETURN;
}

static inline void generate_exception(DisasContext *ctx, int excp)
void generate_exception(DisasContext *ctx, int excp)
{
gen_helper_0e0i(raise_exception, excp);
}

static inline void generate_exception_end(DisasContext *ctx, int excp)
void generate_exception_end(DisasContext *ctx, int excp)
{
generate_exception_err(ctx, excp, 0);
}
Expand Down Expand Up @@ -3013,7 +2991,7 @@ static inline void check_dsp_r3(DisasContext *ctx)
* This code generates a "reserved instruction" exception if the
* CPU does not support the instruction set corresponding to flags.
*/
static inline void check_insn(DisasContext *ctx, uint64_t flags)
void check_insn(DisasContext *ctx, uint64_t flags)
{
if (unlikely(!(ctx->insn_flags & flags))) {
generate_exception_end(ctx, EXCP_RI);
Expand Down Expand Up @@ -3064,7 +3042,7 @@ static inline void check_ps(DisasContext *ctx)
* This code generates a "reserved instruction" exception if 64-bit
* instructions are not enabled.
*/
static inline void check_mips_64(DisasContext *ctx)
void check_mips_64(DisasContext *ctx)
{
if (unlikely(!(ctx->hflags & MIPS_HFLAG_64))) {
generate_exception_end(ctx, EXCP_RI);
Expand Down Expand Up @@ -3390,8 +3368,7 @@ OP_LD_ATOMIC(lld, ld64);
#endif
#undef OP_LD_ATOMIC

static void gen_base_offset_addr(DisasContext *ctx, TCGv addr,
int base, int offset)
void gen_base_offset_addr(DisasContext *ctx, TCGv addr, int base, int offset)
{
if (base == 0) {
tcg_gen_movi_tl(addr, offset);
Expand Down
38 changes: 38 additions & 0 deletions target/mips/translate.h
View file
Expand Up @@ -10,6 +10,8 @@

#include "exec/translator.h"

#define MIPS_DEBUG_DISAS 0

typedef struct DisasContext {
DisasContextBase base;
target_ulong saved_pc;
Expand Down Expand Up @@ -47,4 +49,40 @@ typedef struct DisasContext {
int gi;
} DisasContext;

/* MIPS major opcodes */
#define MASK_OP_MAJOR(op) (op & (0x3F << 26))

void generate_exception(DisasContext *ctx, int excp);
void generate_exception_err(DisasContext *ctx, int excp, int err);
void generate_exception_end(DisasContext *ctx, int excp);
void check_insn(DisasContext *ctx, uint64_t flags);
#ifdef TARGET_MIPS64
void check_mips_64(DisasContext *ctx);
#endif

void gen_base_offset_addr(DisasContext *ctx, TCGv addr, int base, int offset);
void gen_load_gpr(TCGv t, int reg);
void gen_store_gpr(TCGv t, int reg);

extern TCGv cpu_gpr[32], cpu_PC;
extern TCGv bcond;

#define LOG_DISAS(...) \
do { \
if (MIPS_DEBUG_DISAS) { \
qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__); \
} \
} while (0)

#define MIPS_INVAL(op) \
do { \
if (MIPS_DEBUG_DISAS) { \
qemu_log_mask(CPU_LOG_TB_IN_ASM, \
TARGET_FMT_lx ": %08x Invalid %s %03x %03x %03x\n", \
ctx->base.pc_next, ctx->opcode, op, \
ctx->opcode >> 26, ctx->opcode & 0x3F, \
((ctx->opcode >> 16) & 0x1F)); \
} \
} while (0)

#endif

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