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* Add a model of the ETRAX interrupt controller.
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* Clean up the interrupt handling a bit.
* Connect some NOR flash to the test board.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4055 c046a42c-6fe2-441c-8c8c-71466251a162
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edgar_igl committed Mar 14, 2008
1 parent 1ec6d2e commit e62b5b1
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Showing 8 changed files with 323 additions and 179 deletions.
5 changes: 4 additions & 1 deletion Makefile.target
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Expand Up @@ -565,9 +565,12 @@ CPPFLAGS += -DHAS_AUDIO
endif
ifeq ($(TARGET_BASE_ARCH), cris)
OBJS+= etraxfs.o
OBJS+= ptimer.o
OBJS+= etraxfs_pic.o
OBJS+= etraxfs_timer.o
OBJS+= etraxfs_ser.o

OBJS+= ptimer.o
OBJS+= pflash_cfi01.o
endif
ifeq ($(TARGET_BASE_ARCH), sparc)
ifeq ($(TARGET_ARCH), sparc64)
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5 changes: 0 additions & 5 deletions cpu-exec.c
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Expand Up @@ -556,7 +556,6 @@ int cpu_exec(CPUState *env1)
#elif defined(TARGET_CRIS)
if (interrupt_request & CPU_INTERRUPT_HARD) {
do_interrupt(env);
env->interrupt_request &= ~CPU_INTERRUPT_HARD;
BREAK_CHAIN;
}
#elif defined(TARGET_M68K)
Expand Down Expand Up @@ -1181,10 +1180,6 @@ static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
a virtual CPU fault */
cpu_restore_state(tb, env, pc, puc);
}
#if 0
printf("PF exception: NIP=0x%08x error=0x%x %p\n",
env->nip, env->error_code, tb);
#endif
/* we restore the process signal mask as the sigreturn should
do it (XXX: use sigsetjmp) */
sigprocmask(SIG_SETMASK, old_set, NULL);
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121 changes: 31 additions & 90 deletions hw/etraxfs.c
View file
Expand Up @@ -25,99 +25,34 @@
#include <sys/time.h>
#include "hw.h"
#include "sysemu.h"
#include "flash.h"
#include "boards.h"

extern FILE *logfile;

static void main_cpu_reset(void *opaque)
{
CPUState *env = opaque;
cpu_reset(env);
}

static uint32_t fs_mmio_readb (void *opaque, target_phys_addr_t addr)
{
CPUState *env = opaque;
uint32_t r = 0;
printf ("%s %x pc=%x\n", __func__, addr, env->pc);
return r;
}
static uint32_t fs_mmio_readw (void *opaque, target_phys_addr_t addr)
{
CPUState *env = opaque;
uint32_t r = 0;
printf ("%s %x pc=%x\n", __func__, addr, env->pc);
return r;
}

static uint32_t fs_mmio_readl (void *opaque, target_phys_addr_t addr)
{
CPUState *env = opaque;
uint32_t r = 0;
printf ("%s %x p=%x\n", __func__, addr, env->pc);
return r;
}

static void
fs_mmio_writeb (void *opaque, target_phys_addr_t addr, uint32_t value)
{
CPUState *env = opaque;
printf ("%s %x %x pc=%x\n", __func__, addr, value, env->pc);
}
static void
fs_mmio_writew (void *opaque, target_phys_addr_t addr, uint32_t value)
{
CPUState *env = opaque;
printf ("%s %x %x pc=%x\n", __func__, addr, value, env->pc);
}
static void
fs_mmio_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
{
CPUState *env = opaque;
printf ("%s %x %x pc=%x\n", __func__, addr, value, env->pc);
}

static CPUReadMemoryFunc *fs_mmio_read[] = {
&fs_mmio_readb,
&fs_mmio_readw,
&fs_mmio_readl,
};

static CPUWriteMemoryFunc *fs_mmio_write[] = {
&fs_mmio_writeb,
&fs_mmio_writew,
&fs_mmio_writel,
};


/* Init functions for different blocks. */
extern qemu_irq *etraxfs_pic_init(CPUState *env, target_ulong base);
/* TODO: Make these blocks relocate:able. */
extern void etraxfs_timer_init(CPUState *env, qemu_irq *irqs);
extern void etraxfs_ser_init(CPUState *env, qemu_irq *irqs);

void etrax_ack_irq(CPUState *env, uint32_t mask)
{
env->pending_interrupts &= ~mask;
}

static void dummy_cpu_set_irq(void *opaque, int irq, int level)
{
CPUState *env = opaque;

/* Hmm, should this really be done here? */
env->pending_interrupts |= 1 << irq;
cpu_interrupt(env, CPU_INTERRUPT_HARD);
}

static
void bareetraxfs_init (int ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
CPUState *env;
qemu_irq *irqs;
qemu_irq *pic;
int kernel_size;
int internal_regs;
int flash_size = 0x800000;
int index;
ram_addr_t phys_flash;
ram_addr_t phys_ram;

/* init CPUs */
if (cpu_model == NULL) {
Expand All @@ -126,17 +61,31 @@ void bareetraxfs_init (int ram_size, int vga_ram_size,
env = cpu_init(cpu_model);
/* register_savevm("cpu", 0, 3, cpu_save, cpu_load, env); */
qemu_register_reset(main_cpu_reset, env);
irqs = qemu_allocate_irqs(dummy_cpu_set_irq, env, 32);

internal_regs = cpu_register_io_memory(0,
fs_mmio_read, fs_mmio_write, env);
/* 0xb0050000 is the last reg. */
cpu_register_physical_memory (0xac000000, 0x4010000, internal_regs);
/* allocate RAM */
cpu_register_physical_memory(0x40000000, ram_size, IO_MEM_RAM);

etraxfs_timer_init(env, irqs);
etraxfs_ser_init(env, irqs);
phys_ram = qemu_ram_alloc(ram_size);
cpu_register_physical_memory(0x40000000, ram_size, phys_ram | IO_MEM_RAM);
/* Unached mapping. */
cpu_register_physical_memory(0xc0000000, ram_size, phys_ram | IO_MEM_RAM);

phys_flash = qemu_ram_alloc(flash_size);
cpu_register_physical_memory(0,flash_size, IO_MEM_ROM);
cpu_register_physical_memory(0x80000000, flash_size, IO_MEM_ROM);
cpu_register_physical_memory(0x04000000, flash_size, IO_MEM_ROM);
cpu_register_physical_memory(0x84000000, flash_size,
0x04000000 | IO_MEM_ROM);
index = drive_get_index(IF_PFLASH, 0, 0);
pflash_cfi01_register(0x80000000, flash_size,
drives_table[index].bdrv, 65536, flash_size >> 16,
4, 0x0000, 0x0000, 0x0000, 0x0000);
index = drive_get_index(IF_PFLASH, 0, 1);
pflash_cfi01_register(0x84000000, flash_size,
drives_table[index].bdrv, 65536, flash_size >> 16,
4, 0x0000, 0x0000, 0x0000, 0x0000);

pic = etraxfs_pic_init(env, 0xb001c000);
etraxfs_timer_init(env, pic);
etraxfs_ser_init(env, pic);

kernel_size = load_image(kernel_filename, phys_ram_base + 0x4000);
/* magic for boot. */
Expand Down Expand Up @@ -165,14 +114,6 @@ void DMA_run(void)
{
}

void pic_info()
{
}

void irq_info()
{
}

QEMUMachine bareetraxfs_machine = {
"bareetraxfs",
"Bare ETRAX FS board",
Expand Down

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