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tcg/tci: Split out tci_args_rrr
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Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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@rth7680
rth7680 committed Mar 17, 2021
1 parent fc4a62f commit e85e4b8
Showing 1 changed file with 57 additions and 97 deletions.
154 changes: 57 additions & 97 deletions tcg/tci.c
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Expand Up @@ -191,6 +191,14 @@ static void tci_args_rr(const uint8_t **tb_ptr,
*r1 = tci_read_r(tb_ptr);
}

static void tci_args_rrr(const uint8_t **tb_ptr,
TCGReg *r0, TCGReg *r1, TCGReg *r2)
{
*r0 = tci_read_r(tb_ptr);
*r1 = tci_read_r(tb_ptr);
*r2 = tci_read_r(tb_ptr);
}

static void tci_args_rrs(const uint8_t **tb_ptr,
TCGReg *r0, TCGReg *r1, int32_t *i2)
{
Expand Down Expand Up @@ -349,7 +357,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
uint8_t op_size = tb_ptr[1];
const uint8_t *old_code_ptr = tb_ptr;
#endif
TCGReg r0, r1;
TCGReg r0, r1, r2;
tcg_target_ulong t0;
tcg_target_ulong t1;
tcg_target_ulong t2;
Expand Down Expand Up @@ -486,101 +494,71 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
/* Arithmetic operations (mixed 32/64 bit). */

CASE_32_64(add)
t0 = *tb_ptr++;
t1 = tci_read_rval(regs, &tb_ptr);
t2 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, t1 + t2);
tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
regs[r0] = regs[r1] + regs[r2];
break;
CASE_32_64(sub)
t0 = *tb_ptr++;
t1 = tci_read_rval(regs, &tb_ptr);
t2 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, t1 - t2);
tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
regs[r0] = regs[r1] - regs[r2];
break;
CASE_32_64(mul)
t0 = *tb_ptr++;
t1 = tci_read_rval(regs, &tb_ptr);
t2 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, t1 * t2);
tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
regs[r0] = regs[r1] * regs[r2];
break;
CASE_32_64(and)
t0 = *tb_ptr++;
t1 = tci_read_rval(regs, &tb_ptr);
t2 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, t1 & t2);
tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
regs[r0] = regs[r1] & regs[r2];
break;
CASE_32_64(or)
t0 = *tb_ptr++;
t1 = tci_read_rval(regs, &tb_ptr);
t2 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, t1 | t2);
tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
regs[r0] = regs[r1] | regs[r2];
break;
CASE_32_64(xor)
t0 = *tb_ptr++;
t1 = tci_read_rval(regs, &tb_ptr);
t2 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, t1 ^ t2);
tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
regs[r0] = regs[r1] ^ regs[r2];
break;

/* Arithmetic operations (32 bit). */

case INDEX_op_div_i32:
t0 = *tb_ptr++;
t1 = tci_read_rval(regs, &tb_ptr);
t2 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, (int32_t)t1 / (int32_t)t2);
tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
regs[r0] = (int32_t)regs[r1] / (int32_t)regs[r2];
break;
case INDEX_op_divu_i32:
t0 = *tb_ptr++;
t1 = tci_read_rval(regs, &tb_ptr);
t2 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, (uint32_t)t1 / (uint32_t)t2);
tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
regs[r0] = (uint32_t)regs[r1] / (uint32_t)regs[r2];
break;
case INDEX_op_rem_i32:
t0 = *tb_ptr++;
t1 = tci_read_rval(regs, &tb_ptr);
t2 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, (int32_t)t1 % (int32_t)t2);
tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
regs[r0] = (int32_t)regs[r1] % (int32_t)regs[r2];
break;
case INDEX_op_remu_i32:
t0 = *tb_ptr++;
t1 = tci_read_rval(regs, &tb_ptr);
t2 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, (uint32_t)t1 % (uint32_t)t2);
tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
regs[r0] = (uint32_t)regs[r1] % (uint32_t)regs[r2];
break;

/* Shift/rotate operations (32 bit). */

case INDEX_op_shl_i32:
t0 = *tb_ptr++;
t1 = tci_read_rval(regs, &tb_ptr);
t2 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, (uint32_t)t1 << (t2 & 31));
tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
regs[r0] = (uint32_t)regs[r1] << (regs[r2] & 31);
break;
case INDEX_op_shr_i32:
t0 = *tb_ptr++;
t1 = tci_read_rval(regs, &tb_ptr);
t2 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, (uint32_t)t1 >> (t2 & 31));
tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
regs[r0] = (uint32_t)regs[r1] >> (regs[r2] & 31);
break;
case INDEX_op_sar_i32:
t0 = *tb_ptr++;
t1 = tci_read_rval(regs, &tb_ptr);
t2 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, (int32_t)t1 >> (t2 & 31));
tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
regs[r0] = (int32_t)regs[r1] >> (regs[r2] & 31);
break;
#if TCG_TARGET_HAS_rot_i32
case INDEX_op_rotl_i32:
t0 = *tb_ptr++;
t1 = tci_read_rval(regs, &tb_ptr);
t2 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, rol32(t1, t2 & 31));
tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
regs[r0] = rol32(regs[r1], regs[r2] & 31);
break;
case INDEX_op_rotr_i32:
t0 = *tb_ptr++;
t1 = tci_read_rval(regs, &tb_ptr);
t2 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, ror32(t1, t2 & 31));
tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
regs[r0] = ror32(regs[r1], regs[r2] & 31);
break;
#endif
#if TCG_TARGET_HAS_deposit_i32
Expand Down Expand Up @@ -715,62 +693,44 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
/* Arithmetic operations (64 bit). */

case INDEX_op_div_i64:
t0 = *tb_ptr++;
t1 = tci_read_rval(regs, &tb_ptr);
t2 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, (int64_t)t1 / (int64_t)t2);
tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
regs[r0] = (int64_t)regs[r1] / (int64_t)regs[r2];
break;
case INDEX_op_divu_i64:
t0 = *tb_ptr++;
t1 = tci_read_rval(regs, &tb_ptr);
t2 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, (uint64_t)t1 / (uint64_t)t2);
tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
regs[r0] = (uint64_t)regs[r1] / (uint64_t)regs[r2];
break;
case INDEX_op_rem_i64:
t0 = *tb_ptr++;
t1 = tci_read_rval(regs, &tb_ptr);
t2 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, (int64_t)t1 % (int64_t)t2);
tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
regs[r0] = (int64_t)regs[r1] % (int64_t)regs[r2];
break;
case INDEX_op_remu_i64:
t0 = *tb_ptr++;
t1 = tci_read_rval(regs, &tb_ptr);
t2 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, (uint64_t)t1 % (uint64_t)t2);
tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
regs[r0] = (uint64_t)regs[r1] % (uint64_t)regs[r2];
break;

/* Shift/rotate operations (64 bit). */

case INDEX_op_shl_i64:
t0 = *tb_ptr++;
t1 = tci_read_rval(regs, &tb_ptr);
t2 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, t1 << (t2 & 63));
tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
regs[r0] = regs[r1] << (regs[r2] & 63);
break;
case INDEX_op_shr_i64:
t0 = *tb_ptr++;
t1 = tci_read_rval(regs, &tb_ptr);
t2 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, t1 >> (t2 & 63));
tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
regs[r0] = regs[r1] >> (regs[r2] & 63);
break;
case INDEX_op_sar_i64:
t0 = *tb_ptr++;
t1 = tci_read_rval(regs, &tb_ptr);
t2 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, ((int64_t)t1 >> (t2 & 63)));
tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
regs[r0] = (int64_t)regs[r1] >> (regs[r2] & 63);
break;
#if TCG_TARGET_HAS_rot_i64
case INDEX_op_rotl_i64:
t0 = *tb_ptr++;
t1 = tci_read_rval(regs, &tb_ptr);
t2 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, rol64(t1, t2 & 63));
tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
regs[r0] = rol64(regs[r1], regs[r2] & 63);
break;
case INDEX_op_rotr_i64:
t0 = *tb_ptr++;
t1 = tci_read_rval(regs, &tb_ptr);
t2 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, ror64(t1, t2 & 63));
tci_args_rrr(&tb_ptr, &r0, &r1, &r2);
regs[r0] = ror64(regs[r1], regs[r2] & 63);
break;
#endif
#if TCG_TARGET_HAS_deposit_i64
Expand Down

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