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target/hppa: Convert fp indexed memory insns
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Tested-by: Helge Deller <deller@gmx.de>
Tested-by: Sven Schnelle <svens@stackframe.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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@rth7680
rth7680 committed Feb 12, 2019
1 parent 740038d commit e8777db
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Showing 2 changed files with 21 additions and 93 deletions.
21 changes: 21 additions & 0 deletions target/hppa/insns.decode
View file
Expand Up @@ -38,6 +38,7 @@
%sm_imm 16:10 !function=expand_sm_imm

%rm64 1:1 16:5
%rt64 6:1 0:5

%im5_0 0:s1 1:4
%im5_16 16:s1 17:4
Expand Down Expand Up @@ -195,6 +196,26 @@ lda 000011 ..... ..... .. . 0 -- 0110 ...... @ldstx size=2
sta 000011 ..... ..... .. . 1 -- 1110 ...... @stim5 size=2
stby 000011 b:5 r:5 sp:2 a:1 1 -- 1100 m:1 ..... disp=%im5_0

@fldstwx ...... b:5 x:5 sp:2 scale:1 ....... m:1 ..... \
&ldst t=%rt64 disp=0 size=2
@fldstwi ...... b:5 ..... sp:2 . ....... . ..... \
&ldst t=%rt64 disp=%im5_16 m=%ma_to_m x=0 scale=0 size=2

fldw 001001 ..... ..... .. . 0 -- 000 . . ..... @fldstwx
fldw 001001 ..... ..... .. . 1 -- 000 . . ..... @fldstwi
fstw 001001 ..... ..... .. . 0 -- 100 . . ..... @fldstwx
fstw 001001 ..... ..... .. . 1 -- 100 . . ..... @fldstwi

@fldstdx ...... b:5 x:5 sp:2 scale:1 ....... m:1 t:5 \
&ldst disp=0 size=3
@fldstdi ...... b:5 ..... sp:2 . ....... . t:5 \
&ldst disp=%im5_16 m=%ma_to_m x=0 scale=0 size=3

fldd 001011 ..... ..... .. . 0 -- 000 0 . ..... @fldstdx
fldd 001011 ..... ..... .. . 1 -- 000 0 . ..... @fldstdi
fstd 001011 ..... ..... .. . 0 -- 100 0 . ..... @fldstdx
fstd 001011 ..... ..... .. . 1 -- 100 0 . ..... @fldstdi

####
# Offset Mem
####
Expand Down
93 changes: 0 additions & 93 deletions target/hppa/translate.c
View file
Expand Up @@ -855,15 +855,6 @@ static void gen_goto_tb(DisasContext *ctx, int which,
}
}

/* PA has a habit of taking the LSB of a field and using that as the sign,
with the rest of the field becoming the least significant bits. */
static target_sreg low_sextract(uint32_t val, int pos, int len)
{
target_ureg x = -(target_ureg)extract32(val, pos, 1);
x = (x << (len - 1)) | extract32(val, pos + 1, len - 1);
return x;
}

static unsigned assemble_rt64(uint32_t insn)
{
unsigned r1 = extract32(insn, 6, 1);
Expand Down Expand Up @@ -2981,84 +2972,6 @@ static bool trans_ldo(DisasContext *ctx, arg_ldo *a)
return true;
}

static bool trans_copr_w(DisasContext *ctx, uint32_t insn)
{
unsigned t0 = extract32(insn, 0, 5);
unsigned m = extract32(insn, 5, 1);
unsigned t1 = extract32(insn, 6, 1);
unsigned ext3 = extract32(insn, 7, 3);
/* unsigned cc = extract32(insn, 10, 2); */
unsigned i = extract32(insn, 12, 1);
unsigned ua = extract32(insn, 13, 1);
unsigned sp = extract32(insn, 14, 2);
unsigned rx = extract32(insn, 16, 5);
unsigned rb = extract32(insn, 21, 5);
unsigned rt = t1 * 32 + t0;
int modify = (m ? (ua ? -1 : 1) : 0);
int disp, scale;

if (i == 0) {
scale = (ua ? 2 : 0);
disp = 0;
modify = m;
} else {
disp = low_sextract(rx, 0, 5);
scale = 0;
rx = 0;
modify = (m ? (ua ? -1 : 1) : 0);
}

switch (ext3) {
case 0: /* FLDW */
do_floadw(ctx, rt, rb, rx, scale, disp, sp, modify);
break;
case 4: /* FSTW */
do_fstorew(ctx, rt, rb, rx, scale, disp, sp, modify);
break;
default:
return gen_illegal(ctx);
}
return true;
}

static bool trans_copr_dw(DisasContext *ctx, uint32_t insn)
{
unsigned rt = extract32(insn, 0, 5);
unsigned m = extract32(insn, 5, 1);
unsigned ext4 = extract32(insn, 6, 4);
/* unsigned cc = extract32(insn, 10, 2); */
unsigned i = extract32(insn, 12, 1);
unsigned ua = extract32(insn, 13, 1);
unsigned sp = extract32(insn, 14, 2);
unsigned rx = extract32(insn, 16, 5);
unsigned rb = extract32(insn, 21, 5);
int modify = (m ? (ua ? -1 : 1) : 0);
int disp, scale;

if (i == 0) {
scale = (ua ? 3 : 0);
disp = 0;
modify = m;
} else {
disp = low_sextract(rx, 0, 5);
scale = 0;
rx = 0;
modify = (m ? (ua ? -1 : 1) : 0);
}

switch (ext4) {
case 0: /* FLDD */
do_floadd(ctx, rt, rb, rx, scale, disp, sp, modify);
break;
case 8: /* FSTD */
do_fstored(ctx, rt, rb, rx, scale, disp, sp, modify);
break;
default:
return gen_illegal(ctx);
}
return true;
}

static bool do_cmpb(DisasContext *ctx, unsigned r, TCGv_reg in1,
unsigned c, unsigned f, unsigned n, int disp)
{
Expand Down Expand Up @@ -4211,12 +4124,6 @@ static void translate_one(DisasContext *ctx, uint32_t insn)

opc = extract32(insn, 26, 6);
switch (opc) {
case 0x09:
trans_copr_w(ctx, insn);
return;
case 0x0B:
trans_copr_dw(ctx, insn);
return;
case 0x0C:
translate_table(ctx, insn, table_float_0c);
return;
Expand Down

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