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Merge tag 'pull-target-arm-20220530' of https://git.linaro.org/people…
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…/pmaydell/qemu-arm into staging

target-arm queue:
 * docs/system/arm: Add FEAT_HCX to list of emulated features
 * target/arm/hvf: Include missing "cpregs.h"
 * hw/sd/allwinner-sdhost: report FIFO water level as 1 when data ready
 * SVE: refactor to use TRANS/TRANS_FEAT macros and push
   SVE feature check down to individual insn level

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# =MU42
# -----END PGP SIGNATURE-----
# gpg: Signature made Mon 30 May 2022 09:06:05 AM PDT
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [full]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full]

* tag 'pull-target-arm-20220530' of https://git.linaro.org/people/pmaydell/qemu-arm: (117 commits)
  target/arm: Remove aa64_sve check from before disas_sve
  target/arm: Add sve feature check for remaining trans_* functions
  target/arm: Use TRANS_FEAT for do_FMLAL_zzxw
  target/arm: Use TRANS_FEAT for do_FMLAL_zzzw
  target/arm: Use TRANS_FEAT for do_shr_narrow
  target/arm: Use TRANS_FEAT for do_shll_tb
  target/arm: Use TRANS_FEAT for do_narrow_extract
  target/arm: Use TRANS_FEAT for FCMLA_zzxz
  target/arm: Remove assert in trans_FCMLA_zzxz
  target/arm: Use TRANS_FEAT for DO_FPCMP
  target/arm: Use TRANS_FEAT for DO_FP_IMM
  target/arm: Move null function and sve check into do_fp_imm
  target/arm: Use TRANS_FEAT for gen_gvec_fpst_zzzzp
  target/arm: Introduce gen_gvec_fpst_zzzzp
  target/arm: Use TRANS_FEAT for FCADD
  target/arm: Use TRANS_FEAT for gen_gvec_fpst_arg_zpzz
  target/arm: Rename do_zpzz_ptr to gen_gvec_fpst_arg_zpzz
  target/arm: Use TRANS_FEAT for do_ppz_fp
  target/arm: Use TRANS_FEAT for FLOGB
  target/arm: Use TRANS_FEAT for do_frint_mode
  ...

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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@rth7680
rth7680 committed May 30, 2022
2 parents f7a1ea4 + b107117 commit ed72f34
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Showing 8 changed files with 2,158 additions and 3,476 deletions.
1 change: 1 addition & 0 deletions docs/system/arm/emulation.rst
View file
Expand Up @@ -29,6 +29,7 @@ the following architecture extensions:
- FEAT_FRINTTS (Floating-point to integer instructions)
- FEAT_FlagM (Flag manipulation instructions v2)
- FEAT_FlagM2 (Enhancements to flag manipulation instructions)
- FEAT_HCX (Support for the HCRX_EL2 register)
- FEAT_HPDS (Hierarchical permission disables)
- FEAT_I8MM (AArch64 Int8 matrix multiplication instructions)
- FEAT_IDST (ID space trap handling)
Expand Down
7 changes: 7 additions & 0 deletions hw/sd/allwinner-sdhost.c
View file
Expand Up @@ -114,7 +114,9 @@ enum {
};

enum {
SD_STAR_FIFO_EMPTY = (1 << 2),
SD_STAR_CARD_PRESENT = (1 << 8),
SD_STAR_FIFO_LEVEL_1 = (1 << 17),
};

enum {
Expand Down Expand Up @@ -467,6 +469,11 @@ static uint64_t allwinner_sdhost_read(void *opaque, hwaddr offset,
break;
case REG_SD_STAR: /* Status */
res = s->status;
if (sdbus_data_ready(&s->sdbus)) {
res |= SD_STAR_FIFO_LEVEL_1;
} else {
res |= SD_STAR_FIFO_EMPTY;
}
break;
case REG_SD_FWLR: /* FIFO Water Level */
res = s->fifo_wlevel;
Expand Down
1 change: 1 addition & 0 deletions target/arm/hvf/hvf.c
View file
Expand Up @@ -17,6 +17,7 @@
#include "sysemu/hvf_int.h"
#include "sysemu/hw_accel.h"
#include "hvf_arm.h"
#include "cpregs.h"

#include <mach/mach_time.h>

Expand Down
57 changes: 43 additions & 14 deletions target/arm/sve.decode
View file
Expand Up @@ -528,8 +528,14 @@ DUPM 00000101 11 0000 dbm:13 rd:5
FCPY 00000101 .. 01 .... 110 imm:8 ..... @rdn_pg4

# SVE copy integer immediate (predicated)
CPY_m_i 00000101 .. 01 .... 01 . ........ ..... @rdn_pg4 imm=%sh8_i8s
CPY_z_i 00000101 .. 01 .... 00 . ........ ..... @rdn_pg4 imm=%sh8_i8s
{
INVALID 00000101 00 01 ---- 01 1 -------- -----
CPY_m_i 00000101 .. 01 .... 01 . ........ ..... @rdn_pg4 imm=%sh8_i8s
}
{
INVALID 00000101 00 01 ---- 00 1 -------- -----
CPY_z_i 00000101 .. 01 .... 00 . ........ ..... @rdn_pg4 imm=%sh8_i8s
}

### SVE Permute - Extract Group

Expand Down Expand Up @@ -787,16 +793,40 @@ WHILE_ptr 00100101 esz:2 1 rm:5 001 100 rn:5 rw:1 rd:4
FDUP 00100101 esz:2 111 00 1110 imm:8 rd:5

# SVE broadcast integer immediate (unpredicated)
DUP_i 00100101 esz:2 111 00 011 . ........ rd:5 imm=%sh8_i8s
{
INVALID 00100101 00 111 00 011 1 -------- -----
DUP_i 00100101 esz:2 111 00 011 . ........ rd:5 imm=%sh8_i8s
}

# SVE integer add/subtract immediate (unpredicated)
ADD_zzi 00100101 .. 100 000 11 . ........ ..... @rdn_sh_i8u
SUB_zzi 00100101 .. 100 001 11 . ........ ..... @rdn_sh_i8u
SUBR_zzi 00100101 .. 100 011 11 . ........ ..... @rdn_sh_i8u
SQADD_zzi 00100101 .. 100 100 11 . ........ ..... @rdn_sh_i8u
UQADD_zzi 00100101 .. 100 101 11 . ........ ..... @rdn_sh_i8u
SQSUB_zzi 00100101 .. 100 110 11 . ........ ..... @rdn_sh_i8u
UQSUB_zzi 00100101 .. 100 111 11 . ........ ..... @rdn_sh_i8u
{
INVALID 00100101 00 100 000 11 1 -------- -----
ADD_zzi 00100101 .. 100 000 11 . ........ ..... @rdn_sh_i8u
}
{
INVALID 00100101 00 100 001 11 1 -------- -----
SUB_zzi 00100101 .. 100 001 11 . ........ ..... @rdn_sh_i8u
}
{
INVALID 00100101 00 100 011 11 1 -------- -----
SUBR_zzi 00100101 .. 100 011 11 . ........ ..... @rdn_sh_i8u
}
{
INVALID 00100101 00 100 100 11 1 -------- -----
SQADD_zzi 00100101 .. 100 100 11 . ........ ..... @rdn_sh_i8u
}
{
INVALID 00100101 00 100 101 11 1 -------- -----
UQADD_zzi 00100101 .. 100 101 11 . ........ ..... @rdn_sh_i8u
}
{
INVALID 00100101 00 100 110 11 1 -------- -----
SQSUB_zzi 00100101 .. 100 110 11 . ........ ..... @rdn_sh_i8u
}
{
INVALID 00100101 00 100 111 11 1 -------- -----
UQSUB_zzi 00100101 .. 100 111 11 . ........ ..... @rdn_sh_i8u
}

# SVE integer min/max immediate (unpredicated)
SMAX_zzi 00100101 .. 101 000 110 ........ ..... @rdn_i8s
Expand Down Expand Up @@ -1568,10 +1598,9 @@ SQRDCMLAH_zzzz 01000100 esz:2 0 rm:5 0011 rot:2 rn:5 rd:5 ra=%reg_movprfx
USDOT_zzzz 01000100 .. 0 ..... 011 110 ..... ..... @rda_rn_rm

### SVE2 floating point matrix multiply accumulate
{
BFMMLA 01100100 01 1 ..... 111 001 ..... ..... @rda_rn_rm_e0
FMMLA 01100100 .. 1 ..... 111 001 ..... ..... @rda_rn_rm
}
BFMMLA 01100100 01 1 ..... 111 001 ..... ..... @rda_rn_rm_e0
FMMLA_s 01100100 10 1 ..... 111 001 ..... ..... @rda_rn_rm_e0
FMMLA_d 01100100 11 1 ..... 111 001 ..... ..... @rda_rn_rm_e0

### SVE2 Memory Gather Load Group

Expand Down
6 changes: 4 additions & 2 deletions target/arm/sve_helper.c
View file
Expand Up @@ -3382,6 +3382,7 @@ void HELPER(sve_punpk_p)(void *vd, void *vn, uint32_t pred_desc)
void HELPER(NAME)(void *vd, void *vn, void *vm, uint32_t desc) \
{ \
intptr_t oprsz = simd_oprsz(desc); \
intptr_t odd_ofs = simd_data(desc); \
intptr_t i, oprsz_2 = oprsz / 2; \
ARMVectorReg tmp_n, tmp_m; \
/* We produce output faster than we consume input. \
Expand All @@ -3393,8 +3394,9 @@ void HELPER(NAME)(void *vd, void *vn, void *vm, uint32_t desc) \
vm = memcpy(&tmp_m, vm, oprsz_2); \
} \
for (i = 0; i < oprsz_2; i += sizeof(TYPE)) { \
*(TYPE *)(vd + H(2 * i + 0)) = *(TYPE *)(vn + H(i)); \
*(TYPE *)(vd + H(2 * i + sizeof(TYPE))) = *(TYPE *)(vm + H(i)); \
*(TYPE *)(vd + H(2 * i + 0)) = *(TYPE *)(vn + odd_ofs + H(i)); \
*(TYPE *)(vd + H(2 * i + sizeof(TYPE))) = \
*(TYPE *)(vm + odd_ofs + H(i)); \
} \
if (sizeof(TYPE) == 16 && unlikely(oprsz & 16)) { \
memset(vd + oprsz - 16, 0, 16); \
Expand Down
2 changes: 1 addition & 1 deletion target/arm/translate-a64.c
View file
Expand Up @@ -14772,7 +14772,7 @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
unallocated_encoding(s);
break;
case 0x2:
if (!dc_isar_feature(aa64_sve, s) || !disas_sve(s, insn)) {
if (!disas_sve(s, insn)) {
unallocated_encoding(s);
}
break;
Expand Down

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