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qtest: Add functions for accessing devices on Aspeed I2C controller
Add read and write functions for accessing registers of I2C devices connected to the Aspeed I2C controller. Signed-off-by: Stefan Berger <stefanb@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Ninad Palsule <ninad@linux.ibm.com> Acked-by: Thomas Huth <thuth@redhat.com> Message-id: 20230331173051.3857801-2-stefanb@linux.ibm.com
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/* | ||
* Aspeed i2c bus interface for reading from and writing to i2c device registers | ||
* | ||
* Copyright (c) 2023 IBM Corporation | ||
* | ||
* Authors: | ||
* Stefan Berger <stefanb@linux.ibm.com> | ||
* | ||
* This work is licensed under the terms of the GNU GPL, version 2 or later. | ||
* See the COPYING file in the top-level directory. | ||
*/ | ||
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#include "qemu/osdep.h" | ||
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#include "qtest_aspeed.h" | ||
#include "hw/i2c/aspeed_i2c.h" | ||
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static void aspeed_i2c_startup(QTestState *s, uint32_t baseaddr, | ||
uint8_t slave_addr, uint8_t reg) | ||
{ | ||
uint32_t v; | ||
static int once; | ||
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if (!once) { | ||
/* one time: enable master */ | ||
qtest_writel(s, baseaddr + A_I2CC_FUN_CTRL, 0); | ||
v = qtest_readl(s, baseaddr + A_I2CC_FUN_CTRL) | A_I2CD_MASTER_EN; | ||
qtest_writel(s, baseaddr + A_I2CC_FUN_CTRL, v); | ||
once = 1; | ||
} | ||
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/* select device */ | ||
qtest_writel(s, baseaddr + A_I2CD_BYTE_BUF, slave_addr << 1); | ||
qtest_writel(s, baseaddr + A_I2CD_CMD, | ||
A_I2CD_M_START_CMD | A_I2CD_M_RX_CMD); | ||
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/* select the register to write to */ | ||
qtest_writel(s, baseaddr + A_I2CD_BYTE_BUF, reg); | ||
qtest_writel(s, baseaddr + A_I2CD_CMD, A_I2CD_M_TX_CMD); | ||
} | ||
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static uint32_t aspeed_i2c_read_n(QTestState *s, | ||
uint32_t baseaddr, uint8_t slave_addr, | ||
uint8_t reg, size_t nbytes) | ||
{ | ||
uint32_t res = 0; | ||
uint32_t v; | ||
size_t i; | ||
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aspeed_i2c_startup(s, baseaddr, slave_addr, reg); | ||
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for (i = 0; i < nbytes; i++) { | ||
qtest_writel(s, baseaddr + A_I2CD_CMD, A_I2CD_M_RX_CMD); | ||
v = qtest_readl(s, baseaddr + A_I2CD_BYTE_BUF) >> 8; | ||
res |= (v & 0xff) << (i * 8); | ||
} | ||
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qtest_writel(s, baseaddr + A_I2CD_CMD, A_I2CD_M_STOP_CMD); | ||
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return res; | ||
} | ||
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uint32_t aspeed_i2c_readl(QTestState *s, | ||
uint32_t baseaddr, uint8_t slave_addr, uint8_t reg) | ||
{ | ||
return aspeed_i2c_read_n(s, baseaddr, slave_addr, reg, sizeof(uint32_t)); | ||
} | ||
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uint16_t aspeed_i2c_readw(QTestState *s, | ||
uint32_t baseaddr, uint8_t slave_addr, uint8_t reg) | ||
{ | ||
return aspeed_i2c_read_n(s, baseaddr, slave_addr, reg, sizeof(uint16_t)); | ||
} | ||
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uint8_t aspeed_i2c_readb(QTestState *s, | ||
uint32_t baseaddr, uint8_t slave_addr, uint8_t reg) | ||
{ | ||
return aspeed_i2c_read_n(s, baseaddr, slave_addr, reg, sizeof(uint8_t)); | ||
} | ||
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static void aspeed_i2c_write_n(QTestState *s, | ||
uint32_t baseaddr, uint8_t slave_addr, | ||
uint8_t reg, uint32_t v, size_t nbytes) | ||
{ | ||
size_t i; | ||
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aspeed_i2c_startup(s, baseaddr, slave_addr, reg); | ||
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for (i = 0; i < nbytes; i++) { | ||
qtest_writel(s, baseaddr + A_I2CD_BYTE_BUF, v & 0xff); | ||
v >>= 8; | ||
qtest_writel(s, baseaddr + A_I2CD_CMD, A_I2CD_M_TX_CMD); | ||
} | ||
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qtest_writel(s, baseaddr + A_I2CD_CMD, A_I2CD_M_STOP_CMD); | ||
} | ||
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void aspeed_i2c_writel(QTestState *s, | ||
uint32_t baseaddr, uint8_t slave_addr, | ||
uint8_t reg, uint32_t v) | ||
{ | ||
aspeed_i2c_write_n(s, baseaddr, slave_addr, reg, v, sizeof(v)); | ||
} | ||
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void aspeed_i2c_writew(QTestState *s, | ||
uint32_t baseaddr, uint8_t slave_addr, | ||
uint8_t reg, uint16_t v) | ||
{ | ||
aspeed_i2c_write_n(s, baseaddr, slave_addr, reg, v, sizeof(v)); | ||
} | ||
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void aspeed_i2c_writeb(QTestState *s, | ||
uint32_t baseaddr, uint8_t slave_addr, | ||
uint8_t reg, uint8_t v) | ||
{ | ||
aspeed_i2c_write_n(s, baseaddr, slave_addr, reg, v, sizeof(v)); | ||
} |
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@@ -0,0 +1,41 @@ | ||
/* | ||
* Aspeed i2c bus interface to reading and writing to i2c device registers | ||
* | ||
* Copyright (c) 2023 IBM Corporation | ||
* | ||
* Authors: | ||
* Stefan Berger <stefanb@linux.ibm.com> | ||
* | ||
* This work is licensed under the terms of the GNU GPL, version 2 or later. | ||
* See the COPYING file in the top-level directory. | ||
*/ | ||
#ifndef QTEST_ASPEED_H | ||
#define QTEST_ASPEED_H | ||
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#include <stdint.h> | ||
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#include "libqtest.h" | ||
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#define AST2600_ASPEED_I2C_BASE_ADDR 0x1e78a000 | ||
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/* Implements only AST2600 I2C controller */ | ||
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static inline uint32_t ast2600_i2c_calc_bus_addr(uint8_t bus_num) | ||
{ | ||
return AST2600_ASPEED_I2C_BASE_ADDR + 0x80 + bus_num * 0x80; | ||
} | ||
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uint8_t aspeed_i2c_readb(QTestState *s, | ||
uint32_t baseaddr, uint8_t slave_addr, uint8_t reg); | ||
uint16_t aspeed_i2c_readw(QTestState *s, | ||
uint32_t baseaddr, uint8_t slave_addr, uint8_t reg); | ||
uint32_t aspeed_i2c_readl(QTestState *s, | ||
uint32_t baseaddr, uint8_t slave_addr, uint8_t reg); | ||
void aspeed_i2c_writeb(QTestState *s, uint32_t baseaddr, uint8_t slave_addr, | ||
uint8_t reg, uint8_t v); | ||
void aspeed_i2c_writew(QTestState *s, uint32_t baseaddr, uint8_t slave_addr, | ||
uint8_t reg, uint16_t v); | ||
void aspeed_i2c_writel(QTestState *s, uint32_t baseaddr, uint8_t slave_addr, | ||
uint8_t reg, uint32_t v); | ||
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#endif |