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exec: Make stq_*_phys input an AddressSpace
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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
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@edgarigl
edgarigl committed Feb 11, 2014
1 parent 41701aa commit f606604
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Showing 18 changed files with 132 additions and 92 deletions.
12 changes: 6 additions & 6 deletions exec.c
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Expand Up @@ -2683,22 +2683,22 @@ void stw_be_phys(hwaddr addr, uint32_t val)
}

/* XXX: optimize */
void stq_phys(hwaddr addr, uint64_t val)
void stq_phys(AddressSpace *as, hwaddr addr, uint64_t val)
{
val = tswap64(val);
cpu_physical_memory_write(addr, &val, 8);
address_space_rw(as, addr, (void *) &val, 8, 1);
}

void stq_le_phys(hwaddr addr, uint64_t val)
void stq_le_phys(AddressSpace *as, hwaddr addr, uint64_t val)
{
val = cpu_to_le64(val);
cpu_physical_memory_write(addr, &val, 8);
address_space_rw(as, addr, (void *) &val, 8, 1);
}

void stq_be_phys(hwaddr addr, uint64_t val)
void stq_be_phys(AddressSpace *as, hwaddr addr, uint64_t val)
{
val = cpu_to_be64(val);
cpu_physical_memory_write(addr, &val, 8);
address_space_rw(as, addr, (void *) &val, 8, 1);
}

/* virtual memory access for debug (includes writing to ROM) */
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5 changes: 3 additions & 2 deletions hw/alpha/dp264.c
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Expand Up @@ -161,8 +161,9 @@ static void clipper_init(QEMUMachineInitArgs *args)
load_image_targphys(initrd_filename, initrd_base,
ram_size - initrd_base);

stq_phys(param_offset + 0x100, initrd_base + 0xfffffc0000000000ULL);
stq_phys(param_offset + 0x108, initrd_size);
stq_phys(&address_space_memory,
param_offset + 0x100, initrd_base + 0xfffffc0000000000ULL);
stq_phys(&address_space_memory, param_offset + 0x108, initrd_size);
}
}
}
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2 changes: 1 addition & 1 deletion hw/net/vmware_utils.h
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Expand Up @@ -119,7 +119,7 @@ static inline void
vmw_shmem_st64(hwaddr addr, uint64_t value)
{
VMW_SHPRN("SHMEM store64: %" PRIx64 " (value %" PRIx64 ")", addr, value);
stq_le_phys(addr, value);
stq_le_phys(&address_space_memory, addr, value);
}

/* Macros for simplification of operations on array-style registers */
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6 changes: 4 additions & 2 deletions hw/ppc/spapr_hcall.c
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Expand Up @@ -559,6 +559,8 @@ static target_ulong h_logical_load(PowerPCCPU *cpu, sPAPREnvironment *spapr,
static target_ulong h_logical_store(PowerPCCPU *cpu, sPAPREnvironment *spapr,
target_ulong opcode, target_ulong *args)
{
CPUState *cs = CPU(cpu);

target_ulong size = args[0];
target_ulong addr = args[1];
target_ulong val = args[2];
Expand All @@ -574,7 +576,7 @@ static target_ulong h_logical_store(PowerPCCPU *cpu, sPAPREnvironment *spapr,
stl_phys(addr, val);
return H_SUCCESS;
case 8:
stq_phys(addr, val);
stq_phys(cs->as, addr, val);
return H_SUCCESS;
}
return H_PARAMETER;
Expand Down Expand Up @@ -639,7 +641,7 @@ static target_ulong h_logical_memop(PowerPCCPU *cpu, sPAPREnvironment *spapr,
stl_phys(dst, tmp);
break;
case 3:
stq_phys(dst, tmp);
stq_phys(cs->as, dst, tmp);
break;
}
dst = dst + step;
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3 changes: 2 additions & 1 deletion hw/s390x/s390-virtio-bus.c
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Expand Up @@ -378,7 +378,8 @@ void s390_virtio_device_sync(VirtIOS390Device *dev)
vring = s390_virtio_next_ring(bus);
virtio_queue_set_addr(dev->vdev, i, vring);
virtio_queue_set_vector(dev->vdev, i, i);
stq_be_phys(vq + VIRTIO_VQCONFIG_OFFS_ADDRESS, vring);
stq_be_phys(&address_space_memory,
vq + VIRTIO_VQCONFIG_OFFS_ADDRESS, vring);
stw_be_phys(vq + VIRTIO_VQCONFIG_OFFS_NUM, virtio_queue_get_num(dev->vdev, i));
}

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4 changes: 2 additions & 2 deletions hw/s390x/virtio-ccw.c
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Expand Up @@ -873,15 +873,15 @@ static void virtio_ccw_notify(DeviceState *d, uint16_t vector)
}
indicators = ldq_phys(&address_space_memory, dev->indicators);
indicators |= 1ULL << vector;
stq_phys(dev->indicators, indicators);
stq_phys(&address_space_memory, dev->indicators, indicators);
} else {
if (!dev->indicators2) {
return;
}
vector = 0;
indicators = ldq_phys(&address_space_memory, dev->indicators2);
indicators |= 1ULL << vector;
stq_phys(dev->indicators2, indicators);
stq_phys(&address_space_memory, dev->indicators2, indicators);
}

css_conditional_io_interrupt(sch);
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3 changes: 2 additions & 1 deletion hw/scsi/megasas.c
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Expand Up @@ -517,7 +517,8 @@ static void megasas_complete_frame(MegasasState *s, uint64_t context)
tail = s->reply_queue_head;
if (megasas_use_queue64(s)) {
queue_offset = tail * sizeof(uint64_t);
stq_le_phys(s->reply_queue_pa + queue_offset, context);
stq_le_phys(&address_space_memory,
s->reply_queue_pa + queue_offset, context);
} else {
queue_offset = tail * sizeof(uint32_t);
stl_le_phys(s->reply_queue_pa + queue_offset, context);
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6 changes: 3 additions & 3 deletions include/exec/cpu-common.h
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Expand Up @@ -95,8 +95,8 @@ void stw_le_phys(hwaddr addr, uint32_t val);
void stw_be_phys(hwaddr addr, uint32_t val);
void stl_le_phys(hwaddr addr, uint32_t val);
void stl_be_phys(hwaddr addr, uint32_t val);
void stq_le_phys(hwaddr addr, uint64_t val);
void stq_be_phys(hwaddr addr, uint64_t val);
void stq_le_phys(AddressSpace *as, hwaddr addr, uint64_t val);
void stq_be_phys(AddressSpace *as, hwaddr addr, uint64_t val);

#ifdef NEED_CPU_H
uint32_t lduw_phys(AddressSpace *as, hwaddr addr);
Expand All @@ -105,7 +105,7 @@ uint64_t ldq_phys(AddressSpace *as, hwaddr addr);
void stl_phys_notdirty(hwaddr addr, uint32_t val);
void stw_phys(hwaddr addr, uint32_t val);
void stl_phys(hwaddr addr, uint32_t val);
void stq_phys(hwaddr addr, uint64_t val);
void stq_phys(AddressSpace *as, hwaddr addr, uint64_t val);
#endif

void cpu_physical_memory_write_rom(hwaddr addr,
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2 changes: 1 addition & 1 deletion target-alpha/helper.h
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Expand Up @@ -106,7 +106,7 @@ DEF_HELPER_2(ldq_phys, i64, env, i64)
DEF_HELPER_2(ldl_l_phys, i64, env, i64)
DEF_HELPER_2(ldq_l_phys, i64, env, i64)
DEF_HELPER_2(stl_phys, void, i64, i64)
DEF_HELPER_2(stq_phys, void, i64, i64)
DEF_HELPER_3(stq_phys, void, env, i64, i64)
DEF_HELPER_3(stl_c_phys, i64, env, i64, i64)
DEF_HELPER_3(stq_c_phys, i64, env, i64, i64)

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7 changes: 4 additions & 3 deletions target-alpha/mem_helper.c
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Expand Up @@ -55,9 +55,10 @@ void helper_stl_phys(uint64_t p, uint64_t v)
stl_phys(p, v);
}

void helper_stq_phys(uint64_t p, uint64_t v)
void helper_stq_phys(CPUAlphaState *env, uint64_t p, uint64_t v)
{
stq_phys(p, v);
CPUState *cs = ENV_GET_CPU(env);
stq_phys(cs->as, p, v);
}

uint64_t helper_stl_c_phys(CPUAlphaState *env, uint64_t p, uint64_t v)
Expand Down Expand Up @@ -85,7 +86,7 @@ uint64_t helper_stq_c_phys(CPUAlphaState *env, uint64_t p, uint64_t v)
if (p == env->lock_addr) {
uint64_t old = ldq_phys(cs->as, p);
if (old == env->lock_value) {
stq_phys(p, v);
stq_phys(cs->as, p, v);
ret = 1;
}
}
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2 changes: 1 addition & 1 deletion target-alpha/translate.c
View file
Expand Up @@ -3229,7 +3229,7 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn)
break;
case 0x1:
/* Quadword physical access */
gen_helper_stq_phys(addr, val);
gen_helper_stq_phys(cpu_env, addr, val);
break;
case 0x2:
/* Longword physical access with lock */
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3 changes: 2 additions & 1 deletion target-i386/helper.c
View file
Expand Up @@ -881,7 +881,8 @@ int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr,
error_code |= PG_ERROR_I_D_MASK;
if (env->intercept_exceptions & (1 << EXCP0E_PAGE)) {
/* cr2 is not modified in case of exceptions */
stq_phys(env->vm_vmcb + offsetof(struct vmcb, control.exit_info_2),
stq_phys(cs->as,
env->vm_vmcb + offsetof(struct vmcb, control.exit_info_2),
addr);
} else {
env->cr[2] = addr;
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33 changes: 17 additions & 16 deletions target-i386/smm_helper.c
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Expand Up @@ -43,6 +43,7 @@ void helper_rsm(CPUX86State *env)
void do_smm_enter(X86CPU *cpu)
{
CPUX86State *env = &cpu->env;
CPUState *cs = CPU(cpu);
target_ulong sm_state;
SegmentCache *dt;
int i, offset;
Expand All @@ -62,39 +63,39 @@ void do_smm_enter(X86CPU *cpu)
stw_phys(sm_state + offset, dt->selector);
stw_phys(sm_state + offset + 2, (dt->flags >> 8) & 0xf0ff);
stl_phys(sm_state + offset + 4, dt->limit);
stq_phys(sm_state + offset + 8, dt->base);
stq_phys(cs->as, sm_state + offset + 8, dt->base);
}

stq_phys(sm_state + 0x7e68, env->gdt.base);
stq_phys(cs->as, sm_state + 0x7e68, env->gdt.base);
stl_phys(sm_state + 0x7e64, env->gdt.limit);

stw_phys(sm_state + 0x7e70, env->ldt.selector);
stq_phys(sm_state + 0x7e78, env->ldt.base);
stq_phys(cs->as, sm_state + 0x7e78, env->ldt.base);
stl_phys(sm_state + 0x7e74, env->ldt.limit);
stw_phys(sm_state + 0x7e72, (env->ldt.flags >> 8) & 0xf0ff);

stq_phys(sm_state + 0x7e88, env->idt.base);
stq_phys(cs->as, sm_state + 0x7e88, env->idt.base);
stl_phys(sm_state + 0x7e84, env->idt.limit);

stw_phys(sm_state + 0x7e90, env->tr.selector);
stq_phys(sm_state + 0x7e98, env->tr.base);
stq_phys(cs->as, sm_state + 0x7e98, env->tr.base);
stl_phys(sm_state + 0x7e94, env->tr.limit);
stw_phys(sm_state + 0x7e92, (env->tr.flags >> 8) & 0xf0ff);

stq_phys(sm_state + 0x7ed0, env->efer);
stq_phys(cs->as, sm_state + 0x7ed0, env->efer);

stq_phys(sm_state + 0x7ff8, env->regs[R_EAX]);
stq_phys(sm_state + 0x7ff0, env->regs[R_ECX]);
stq_phys(sm_state + 0x7fe8, env->regs[R_EDX]);
stq_phys(sm_state + 0x7fe0, env->regs[R_EBX]);
stq_phys(sm_state + 0x7fd8, env->regs[R_ESP]);
stq_phys(sm_state + 0x7fd0, env->regs[R_EBP]);
stq_phys(sm_state + 0x7fc8, env->regs[R_ESI]);
stq_phys(sm_state + 0x7fc0, env->regs[R_EDI]);
stq_phys(cs->as, sm_state + 0x7ff8, env->regs[R_EAX]);
stq_phys(cs->as, sm_state + 0x7ff0, env->regs[R_ECX]);
stq_phys(cs->as, sm_state + 0x7fe8, env->regs[R_EDX]);
stq_phys(cs->as, sm_state + 0x7fe0, env->regs[R_EBX]);
stq_phys(cs->as, sm_state + 0x7fd8, env->regs[R_ESP]);
stq_phys(cs->as, sm_state + 0x7fd0, env->regs[R_EBP]);
stq_phys(cs->as, sm_state + 0x7fc8, env->regs[R_ESI]);
stq_phys(cs->as, sm_state + 0x7fc0, env->regs[R_EDI]);
for (i = 8; i < 16; i++) {
stq_phys(sm_state + 0x7ff8 - i * 8, env->regs[i]);
stq_phys(cs->as, sm_state + 0x7ff8 - i * 8, env->regs[i]);
}
stq_phys(sm_state + 0x7f78, env->eip);
stq_phys(cs->as, sm_state + 0x7f78, env->eip);
stl_phys(sm_state + 0x7f70, cpu_compute_eflags(env));
stl_phys(sm_state + 0x7f68, env->dr[6]);
stl_phys(sm_state + 0x7f60, env->dr[7]);
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