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target/ppc: Split out float_invalid_op_div
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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@rth7680 @dgibson
rth7680 authored and dgibson committed Nov 8, 2018
1 parent 4f0da70 commit fec59ef
Showing 1 changed file with 24 additions and 28 deletions.
52 changes: 24 additions & 28 deletions target/ppc/fpu_helper.c
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Expand Up @@ -715,6 +715,21 @@ float64 helper_fmul(CPUPPCState *env, float64 arg1, float64 arg2)
return ret;
}

static void float_invalid_op_div(CPUPPCState *env, bool set_fprc,
uintptr_t retaddr, int classes)
{
classes &= ~is_neg;
if (classes == is_inf) {
/* Division of infinity by infinity */
float_invalid_op_vxidi(env, set_fprc, retaddr);
} else if (classes == is_zero) {
/* Division of zero by zero */
float_invalid_op_vxzdz(env, set_fprc, retaddr);
} else if (classes & is_snan) {
float_invalid_op_vxsnan(env, retaddr);
}
}

/* fdiv - fdiv. */
float64 helper_fdiv(CPUPPCState *env, float64 arg1, float64 arg2)
{
Expand All @@ -723,18 +738,9 @@ float64 helper_fdiv(CPUPPCState *env, float64 arg1, float64 arg2)

if (unlikely(status)) {
if (status & float_flag_invalid) {
/* Determine what kind of invalid operation was seen. */
if (float64_is_infinity(arg1) && float64_is_infinity(arg2)) {
/* Division of infinity by infinity */
float_invalid_op_vxidi(env, 1, GETPC());
} else if (float64_is_zero(arg1) && float64_is_zero(arg2)) {
/* Division of zero by zero */
float_invalid_op_vxzdz(env, 1, GETPC());
} else if (float64_is_signaling_nan(arg1, &env->fp_status) ||
float64_is_signaling_nan(arg2, &env->fp_status)) {
/* sNaN division */
float_invalid_op_vxsnan(env, GETPC());
}
float_invalid_op_div(env, 1, GETPC(),
float64_classify(arg1) |
float64_classify(arg2));
}
if (status & float_flag_divbyzero) {
float_zero_divide_excp(env, GETPC());
Expand Down Expand Up @@ -1969,14 +1975,9 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \
env->fp_status.float_exception_flags |= tstat.float_exception_flags; \
\
if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \
if (tp##_is_infinity(xa.fld) && tp##_is_infinity(xb.fld)) { \
float_invalid_op_vxidi(env, sfprf, GETPC()); \
} else if (tp##_is_zero(xa.fld) && tp##_is_zero(xb.fld)) { \
float_invalid_op_vxzdz(env, sfprf, GETPC()); \
} else if (tp##_is_signaling_nan(xa.fld, &tstat) || \
tp##_is_signaling_nan(xb.fld, &tstat)) { \
float_invalid_op_vxsnan(env, GETPC()); \
} \
float_invalid_op_div(env, sfprf, GETPC(), \
tp##_classify(xa.fld) | \
tp##_classify(xb.fld)); \
} \
if (unlikely(tstat.float_exception_flags & float_flag_divbyzero)) { \
float_zero_divide_excp(env, GETPC()); \
Expand Down Expand Up @@ -2020,14 +2021,9 @@ void helper_xsdivqp(CPUPPCState *env, uint32_t opcode)
env->fp_status.float_exception_flags |= tstat.float_exception_flags;

if (unlikely(tstat.float_exception_flags & float_flag_invalid)) {
if (float128_is_infinity(xa.f128) && float128_is_infinity(xb.f128)) {
float_invalid_op_vxidi(env, 1, GETPC());
} else if (float128_is_zero(xa.f128) && float128_is_zero(xb.f128)) {
float_invalid_op_vxzdz(env, 1, GETPC());
} else if (float128_is_signaling_nan(xa.f128, &tstat) ||
float128_is_signaling_nan(xb.f128, &tstat)) {
float_invalid_op_vxsnan(env, GETPC());
}
float_invalid_op_div(env, 1, GETPC(),
float128_classify(xa.f128) |
float128_classify(xb.f128));
}
if (unlikely(tstat.float_exception_flags & float_flag_divbyzero)) {
float_zero_divide_excp(env, GETPC());
Expand Down

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