Skip to content
A simple RISC-V core, described with Verilog
Branch: master
Clone or download
qmn Restructure directory for clean simulation
* Run make sim-{xilinx,icarus} from hardware/ to simulate execution of
  the hex file in hardware/sim/mem.hex.
Latest commit c978f2e Jun 2, 2013
Permalink
Type Name Latest commit message Commit time
Failed to load latest commit information.
hardware Restructure directory for clean simulation Jun 1, 2013
software/tests Add support for Xilinx ISim Jun 1, 2013
LICENSE Add somewhat working core May 18, 2013
README Add somewhat working core May 18, 2013

README

riscv-invicta
Author: Quan Nguyen - [first][last]@berkeley.edu


                   O o o
                ||
                ||
      ________n_||
      |  __  /__ |
      |_/xx\_/xx\|
        \__/ \__/
=========================
(Image source: Wikipedia)


riscv-invicta is a simple 32-bit, one-stage, in-order RISC-V core.

You can’t perform that action at this time.