Compilation fails on mips32 / mips32el with JIT enabled

[mitya57]

On Debian, we get this failure when compiling on 32-bit MIPS, both big- and little-endian:

LowLevelInterpreter.s:3120: Error: float register should be even, was 3
LowLevelInterpreter.s:3124: Error: float register should be even, was 1
LowLevelInterpreter.s:3140: Error: float register should be even, was 3
LowLevelInterpreter.s:3227: Error: float register should be even, was 3
LowLevelInterpreter.s:3231: Error: float register should be even, was 1
... (and 34 similar errors)

This code comes from generated LLIntAssembly.h. For example, the first line (3120) matches this line:

  OFFLINE_ASM_LOCAL_LABEL(_offlineasm_binaryOp__binaryOpCustomStore__op1NotIntOp2Double)
    "\tmtc1 $v1, $f2\n"                                      // /home/mitya57/qtwebkit-5.212.0-alpha2/Source/JavaScriptCore/llint/LowLevelInterpreter32_64.asm:1012
>>> "\tmtc1 $t3, $f3\n"

LLIntAssembly.h is in turn generated by ruby from LowLevelInterpreter32_64.asm. In all cases I checked, the error was in pairs of tmtc1 instructions (and always in the latter instruction) which are generated from single fii2d instructions in LowLevelInterpreter32_64.asm.

The original instruction for the above pair is fii2d t1, t3, ft1 (line 1012).

The code for processing fii2d instruction is in mips.rb:

        when "fii2d"
            $asm.puts "mtc1 #{operands[0].mipsOperand}, #{operands[2].mipsSingleLo}"
            $asm.puts "mtc1 #{operands[1].mipsOperand}, #{operands[2].mipsSingleHi}"

Here operands[2].mipsSingleHi converts ft2 to $f3 and ft0 to $f1, which looks incorrect.

I checked the upstream webkit code and it is the same. I think we will just disable JIT for now, but I am leaving this report here for reference. If you have any ideas how to fix it, please let me know.

[annulen]

Strange, it builds and works fine on MIPS here

[annulen]

Maybe it's because your toolchain (or build script) adds -mno-odd-spreg by default

https://www.linux-mips.org/archives/linux-mips/2017-06/msg00516.html

[mitya57]

It looks like as gets called only with these options: -v -EL -mips32r2 -O1 -no-mdebug -mabi=32 -march=mips32r2 -mfpxx -KPIC.

[annulen]

https://bugs.debian.org/cgi-bin/bugreport.cgi?bug=795845

This has happened because in GCC 5 the MIPS ABI was altered very
slightly by enabling the -mfpxx GCC option by default. When this option
is enabled, the use of odd numbered floating point registers is not
allowed.

Looks like it's worth fixing, at least for efficiency reasons

[mitya57]

Thanks for the pointer! If you have any idea for the fix, I will be happy to test it.

[annulen]

Easy workaround is to add -modd-spreg flag

[mitya57]

I am not sure if it is safe to add, provided that it breaks the new ABI.

[mitya57]

From @jcowgill on IRC:

<jcowgill> mitya57: using '-moddspreg -mfpxx' will break on newer mips cores
<jcowgill> use -fp32 without any oddspreg flags if you must workaround this
<jcowgill> of course the correct fix is to port the code to fpxx...
<jcowgill> actually i think mips32r2 implements FR1 so using -moddspreg might even break on the buildds (depending on other factors)

I will try to build with -mfp32 now (upd: it works).