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Partail code review (comments, tabs, indentation)
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@quasipedia
quasipedia committed May 25, 2011
1 parent c3c4358 commit 50881b5
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1 change: 1 addition & 0 deletions .gitignore
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*~
*.s
*.sh
*.o
*.hex
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10 changes: 5 additions & 5 deletions config-erl.h
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;; Matrix:
;; K L O C K A N X Ä R
;; 0 0 0 1 1 1 2 2 2
;;
;;
;; X T J U G O F E M X
;; 3 3 3 4 4 5 5 5
;;
;;
;; T I O K V A R T X I
;; 6 6 6 7 7 7 8 8 9
;;
;;
;; X Ö V E R X H A L V
;; a a a b c c c d
;;
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;;
;; S J U T O L V N I O
;;1a1a1a1b1b1b1c1d1d1d
;;
;;
;; Want structure to map minutes past the hour to strings to light
;; 0 -> <none>
;; 1 -> 5, a, b
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;; 9 -> 7, 8, 9
;; 10-> 6, 9
;; 11-> 5, 9

.equ NUMBER_TLC_CHIPS, 2
.global NUMBER_TLC_CHIPS

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184 changes: 92 additions & 92 deletions m168.h
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;***** Created: 2010-02-25 11:46 ******* Source: ATmega168.xml ***********
;*************************************************************************
;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y
;*
;*
;* Number : AVR000
;* File Name : "m168def.inc"
;* Title : Register/Bit Definitions for the ATmega168
;* Date : 2010-02-25
;* Version : 2.35
;* Support E-mail : avr@atmel.com
;* Target MCU : ATmega168
;*
;*
;* DESCRIPTION
;* When including this file in the assembly program file, all I/O register
;* When including this file in the assembly program file, all I/O register
;* names and I/O register bit names appearing in the data book can be used.
;* In addition, the six registers forming the three data pointers X, Y and
;* Z have been assigned names XL - ZH. Highest RAM address for Internal
;* SRAM is also defined
;*
;* In addition, the six registers forming the three data pointers X, Y and
;* Z have been assigned names XL - ZH. Highest RAM address for Internal
;* SRAM is also defined
;*
;* The Register names are represented by their hexadecimal address.
;*
;*
;* The Register Bit names are represented by their bit number (0-7).
;*
;*
;* Please observe the difference in using the bit names with instructions
;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc"
;* (skip if bit in register set/cleared). The following example illustrates
;* this:
;*
;*
;* in r16,PORTB ;read PORTB latch
;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#)
;* out PORTB,r16 ;output to PORTB
;*
;*
;* in r16,TIFR ;read the Timer Interrupt Flag Register
;* sbrc r16,TOV0 ;test the overflow flag (use bit#)
;* rjmp TOV0_is_set ;jump if set
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; ***** TWI **************************
; TWAMR - TWI (Slave) Address Mask Register
.equ TWAM0 , 1 ;
.equ TWAM0 , 1 ;
.equ TWAMR0 , TWAM0 ; For compatibility
.equ TWAM1 , 2 ;
.equ TWAM1 , 2 ;
.equ TWAMR1 , TWAM1 ; For compatibility
.equ TWAM2 , 3 ;
.equ TWAM2 , 3 ;
.equ TWAMR2 , TWAM2 ; For compatibility
.equ TWAM3 , 4 ;
.equ TWAM3 , 4 ;
.equ TWAMR3 , TWAM3 ; For compatibility
.equ TWAM4 , 5 ;
.equ TWAM4 , 5 ;
.equ TWAMR4 , TWAM4 ; For compatibility
.equ TWAM5 , 6 ;
.equ TWAM5 , 6 ;
.equ TWAMR5 , TWAM5 ; For compatibility
.equ TWAM6 , 7 ;
.equ TWAM6 , 7 ;
.equ TWAMR6 , TWAM6 ; For compatibility

; TWBR - TWI Bit Rate register
.equ TWBR0 , 0 ;
.equ TWBR1 , 1 ;
.equ TWBR2 , 2 ;
.equ TWBR3 , 3 ;
.equ TWBR4 , 4 ;
.equ TWBR5 , 5 ;
.equ TWBR6 , 6 ;
.equ TWBR7 , 7 ;
.equ TWBR0 , 0 ;
.equ TWBR1 , 1 ;
.equ TWBR2 , 2 ;
.equ TWBR3 , 3 ;
.equ TWBR4 , 4 ;
.equ TWBR5 , 5 ;
.equ TWBR6 , 6 ;
.equ TWBR7 , 7 ;

; TWCR - TWI Control Register
.equ TWIE , 0 ; TWI Interrupt Enable
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.equ ICNC1 , 7 ; Input Capture 1 Noise Canceler

; TCCR1C - Timer/Counter1 Control Register C
.equ FOC1B , 6 ;
.equ FOC1A , 7 ;
.equ FOC1B , 6 ;
.equ FOC1A , 7 ;

; GTCCR - General Timer/Counter Control Register
.equ PSRSYNC , 0 ; Prescaler Reset Timer/Counter1 and Timer/Counter0
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.equ ADTS0 , 0 ; ADC Auto Trigger Source bit 0
.equ ADTS1 , 1 ; ADC Auto Trigger Source bit 1
.equ ADTS2 , 2 ; ADC Auto Trigger Source bit 2
.equ ACME , 6 ;
.equ ACME , 6 ;

; ADCH - ADC Data Register High Byte
.equ ADCH0 , 0 ; ADC Data Register High Byte Bit 0
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.equ ADCL7 , 7 ; ADC Data Register Low Byte Bit 7

; DIDR0 - Digital Input Disable Register
.equ ADC0D , 0 ;
.equ ADC1D , 1 ;
.equ ADC2D , 2 ;
.equ ADC3D , 3 ;
.equ ADC4D , 4 ;
.equ ADC5D , 5 ;
.equ ADC0D , 0 ;
.equ ADC1D , 1 ;
.equ ADC2D , 2 ;
.equ ADC3D , 3 ;
.equ ADC4D , 4 ;
.equ ADC5D , 5 ;


; ***** ANALOG_COMPARATOR ************
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.equ CS00 , 0 ; Clock Select
.equ CS01 , 1 ; Clock Select
.equ CS02 , 2 ; Clock Select
.equ WGM02 , 3 ;
.equ WGM02 , 3 ;
.equ FOC0B , 6 ; Force Output Compare B
.equ FOC0A , 7 ; Force Output Compare A

; TCNT0 - Timer/Counter0
.equ TCNT0_0 , 0 ;
.equ TCNT0_1 , 1 ;
.equ TCNT0_2 , 2 ;
.equ TCNT0_3 , 3 ;
.equ TCNT0_4 , 4 ;
.equ TCNT0_5 , 5 ;
.equ TCNT0_6 , 6 ;
.equ TCNT0_7 , 7 ;
.equ TCNT0_0 , 0 ;
.equ TCNT0_1 , 1 ;
.equ TCNT0_2 , 2 ;
.equ TCNT0_3 , 3 ;
.equ TCNT0_4 , 4 ;
.equ TCNT0_5 , 5 ;
.equ TCNT0_6 , 6 ;
.equ TCNT0_7 , 7 ;

; OCR0A - Timer/Counter0 Output Compare Register
.equ OCR0A_0 , 0 ;
.equ OCR0A_1 , 1 ;
.equ OCR0A_2 , 2 ;
.equ OCR0A_3 , 3 ;
.equ OCR0A_4 , 4 ;
.equ OCR0A_5 , 5 ;
.equ OCR0A_6 , 6 ;
.equ OCR0A_7 , 7 ;
.equ OCR0A_0 , 0 ;
.equ OCR0A_1 , 1 ;
.equ OCR0A_2 , 2 ;
.equ OCR0A_3 , 3 ;
.equ OCR0A_4 , 4 ;
.equ OCR0A_5 , 5 ;
.equ OCR0A_6 , 6 ;
.equ OCR0A_7 , 7 ;

; OCR0B - Timer/Counter0 Output Compare Register
.equ OCR0B_0 , 0 ;
.equ OCR0B_1 , 1 ;
.equ OCR0B_2 , 2 ;
.equ OCR0B_3 , 3 ;
.equ OCR0B_4 , 4 ;
.equ OCR0B_5 , 5 ;
.equ OCR0B_6 , 6 ;
.equ OCR0B_7 , 7 ;
.equ OCR0B_0 , 0 ;
.equ OCR0B_1 , 1 ;
.equ OCR0B_2 , 2 ;
.equ OCR0B_3 , 3 ;
.equ OCR0B_4 , 4 ;
.equ OCR0B_5 , 5 ;
.equ OCR0B_6 , 6 ;
.equ OCR0B_7 , 7 ;

; GTCCR - General Timer/Counter Control Register
;.equ PSRSYNC , 0 ; Prescaler Reset Timer/Counter1 and Timer/Counter0
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.equ SPMIE , 7 ; SPM Interrupt Enable

; MCUCR - MCU Control Register
.equ IVCE , 0 ;
.equ IVSEL , 1 ;
.equ PUD , 4 ;
.equ IVCE , 0 ;
.equ IVSEL , 1 ;
.equ PUD , 4 ;

; MCUSR - MCU Status Register
.equ PORF , 0 ; Power-on reset flag
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.equ BORF , 2 ; Brown-out Reset Flag
.equ WDRF , 3 ; Watchdog Reset Flag

; SMCR -
.equ SE , 0 ;
.equ SM0 , 1 ;
.equ SM1 , 2 ;
.equ SM2 , 3 ;
; SMCR -
.equ SE , 0 ;
.equ SM0 , 1 ;
.equ SM1 , 2 ;
.equ SM2 , 3 ;

; GPIOR2 - General Purpose I/O Register 2
.equ GPIOR20 , 0 ;
.equ GPIOR21 , 1 ;
.equ GPIOR22 , 2 ;
.equ GPIOR23 , 3 ;
.equ GPIOR24 , 4 ;
.equ GPIOR25 , 5 ;
.equ GPIOR26 , 6 ;
.equ GPIOR27 , 7 ;
.equ GPIOR20 , 0 ;
.equ GPIOR21 , 1 ;
.equ GPIOR22 , 2 ;
.equ GPIOR23 , 3 ;
.equ GPIOR24 , 4 ;
.equ GPIOR25 , 5 ;
.equ GPIOR26 , 6 ;
.equ GPIOR27 , 7 ;

; GPIOR1 - General Purpose I/O Register 1
.equ GPIOR10 , 0 ;
.equ GPIOR11 , 1 ;
.equ GPIOR12 , 2 ;
.equ GPIOR13 , 3 ;
.equ GPIOR14 , 4 ;
.equ GPIOR15 , 5 ;
.equ GPIOR16 , 6 ;
.equ GPIOR17 , 7 ;
.equ GPIOR10 , 0 ;
.equ GPIOR11 , 1 ;
.equ GPIOR12 , 2 ;
.equ GPIOR13 , 3 ;
.equ GPIOR14 , 4 ;
.equ GPIOR15 , 5 ;
.equ GPIOR16 , 6 ;
.equ GPIOR17 , 7 ;

; GPIOR0 - General Purpose I/O Register 0
.equ GPIOR00 , 0 ;
.equ GPIOR01 , 1 ;
.equ GPIOR02 , 2 ;
.equ GPIOR03 , 3 ;
.equ GPIOR04 , 4 ;
.equ GPIOR05 , 5 ;
.equ GPIOR06 , 6 ;
.equ GPIOR07 , 7 ;
.equ GPIOR00 , 0 ;
.equ GPIOR01 , 1 ;
.equ GPIOR02 , 2 ;
.equ GPIOR03 , 3 ;
.equ GPIOR04 , 4 ;
.equ GPIOR05 , 5 ;
.equ GPIOR06 , 6 ;
.equ GPIOR07 , 7 ;

; PRR - Power Reduction Register
.equ PRADC , 0 ; Power Reduction ADC
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4 changes: 2 additions & 2 deletions makefile
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Expand Up @@ -17,6 +17,6 @@ wordClock.hex: wordClock

flash: wordClock.hex
avrdude -c usbasp -p m168 -P /dev/parport0 -U flash:w:wordClock.hex

clean:
rm *.o *.hex wordClock
rm *.o *.hex *.s wordClock

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