Introduce a tier-1 JIT compiler based on aarch64 architecture

We follow the template and API of X64 to implement A64 tier-1 JIT compiler.

* Perfromance
| Metric   | rv32emu-T1C | qemu  |
|----------+-------------+-------|
|aes	   |        0.034|  0.045|
|puzzle	   |       0.0115| 0.0169|
|pi        |        0.035|  0.032|
|dhrystone |	    1.914|  2.005|
|Nqeueens  |	     3.87|  2.898|
|qsort-O2  |	    7.819| 11.614|
|miniz-O2  |	    7.604|  3.803|
|primes-O2 |	   10.551|  5.986|
|sha512-O2 |	    6.497|  2.853|
|stream	   |        52.25| 45.776|

As demonstrated in the memory usage analysis below, the tier-1 JIT
compiler utilizes less memory than QEMU across all benchmarks.

* Memory usage
| Metric   | rv32emu-T1C |   qemu  |
|----------+-------------+---------|
|aes	   |      183,212|1,265,962|
|puzzle	   |      145,239|  891,357|
|pi        |      144,739|  872,525|
|dhrystone |	  146,282|  853,256|
|Nqeueens  |	  146,696|  854,174|
|qsort-O2  |	  146,907|  856,721|
|miniz-O2  |	  157,475|  999,897|
|primes-O2 |	  142,356|  851,661|
|sha512-O2 |	  145,369|  901,136|
|stream	   |      157,975|  955,809|

Related: sysprog21#238

Makefile

@@ -121,15 +121,16 @@ endif
 ENABLE_JIT ?= 0
 $(call set-feature, JIT)
 ifeq ($(call has, JIT), 1)
-OBJS_EXT += jit_x64.o 
-ifneq ($(processor), x86_64)
-$(error JIT mode only supports for x64 target currently.)
+OBJS_EXT += jit.o 
+supported_processor = x86_64 arm64 aarch64
+ifneq ($(processor), $(findstring $(processor), $(supported_processor)))
+$(error JIT mode only supports for x64 and arm64 target currently.)
 endif
 
 src/rv32_jit_template.c:
 	$(Q)tools/gen-jit-template.py $(CFLAGS) > $@
 
-$(OUT)/jit_x64.o: src/jit_x64.c src/rv32_jit_template.c
+$(OUT)/jit.o: src/jit.c src/rv32_jit_template.c
 	$(VECHO) "  CC\t$@\n"
 	$(Q)$(CC) -o $@ $(CFLAGS) -c -MMD -MF $@.d $<
 endif

src/emulate.c

@@ -27,7 +27,7 @@ extern struct target_ops gdbstub_ops;
 
 #if RV32_HAS(JIT)
 #include "cache.h"
-#include "jit_x64.h"
+#include "jit.h"
 #endif
 
 /* Shortcuts for comparing each field of specified RISC-V instruction */
@@ -1067,7 +1067,7 @@ void rv_step(riscv_t *rv, int32_t cycles)
                    cache_freq(rv->block_cache, block->pc_start) >= 1024) ||
                   cache_hot(rv->block_cache, block->pc_start))) {
             block->hot = true;
-            block->offset = translate_x64(rv, block);
+            block->offset = translate_JIT(rv, block);
             ((exec_block_func_t) state->buf)(
                 rv, (uintptr_t) (state->buf + block->offset));
             prev = NULL;