Subcircuits not working for Verilog

[tomhajjar]

I found some old Qucs Verilog BSIM3 n-ch and p-ch files that seem to work even with the parsing issue. Data accuracy wasn't a concern. I'm going to test more old Qucs Verilog examples.

One issue that came up was subcircuits made with Verilog devices won't work. They did work under Qucs. It seems Qucs-S is creating a bad netlist causing ngspice to process the Verilog pmos and nmos devices in the subcircuit like regular Spice pmos/nmos models and flags an error because it doesn't recognize the devices.

Verilog-A_BSIM3_prj.zip

[ra3xdh]

This was already reported and fixed in the source. See #356 The fix will be available since the next release. Closing as duplicate.