Cache Simulator

Configurable CPU cache simulator with LRU replacement policy. Full description here.

Input pattern

<block size> - <architecture> - <associativity> - <write hit policy> - <write miss policy>
<cache(s) size>
<request type> <address> <optional description - will be ignored>

<block size>: Should be in power of 2
<architecture>: 0 for von Neumann (unified I-D cache) - 1 for Harvard (split I-D cache)
<associativity>: Should be in power of 2
<write hit policy>: wt for Write Through - wb for Write Back
<write miss policy>: wa for Write Allocate - nw for No Write Allocate (Write Around)
<cache(s) size>: Should be in power of 2. Separated by - in case of Harvard architecture
<request type>:

type	description
0	data read request
1	data write request
2	instruction read request

Sample input

16 - 1 - 1 - wb - wa
128 - 128
0 00000 data read miss (compulsory)
2 10000 instruction miss (compulsory, replaces 00000 if assoc=1 & unified)
2 20000 instruction miss (compulsory, replaces 00000 if assoc=2 & unified)
2 30000 instruction miss (compulsory, replaces 00000 if assoc=2 & unified)
2 40000 instruction miss (compulsory, replaces 00000 if assoc=4 & unified)
0 00000 data read miss (miss if assoc=1 & unified)
2 10001 instruction miss (miss if assoc=1 & unified)

Sample output

***CACHE SETTINGS***
Split I- D-cache
I-cache size: 128
D-cache size: 128
Associativity: 1
Block size: 16
Write policy: WRITE BACK
Allocation policy: WRITE ALLOCATE

***CACHE STATISTICS***
INSTRUCTIONS
accesses: 5
misses: 5
miss rate: 1.0000 (hit rate 0.0000)
replace: 4
DATA
accesses: 2
misses: 1
miss rate: 0.5000 (hit rate 0.5000)
replace: 0
TRAFFIC (in words)
demand fetch: 24
copies back: 0