forked from DragonFlyBSD/DragonFlyBSD
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advlib.c
2066 lines (1793 loc) · 53 KB
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advlib.c
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/*
* Low level routines for the Advanced Systems Inc. SCSI controllers chips
*
* Copyright (c) 1996-1997, 1999-2000 Justin Gibbs.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions, and the following disclaimer,
* without modification, immediately at the beginning of the file.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD: src/sys/dev/advansys/advlib.c,v 1.15.2.1 2000/04/14 13:32:49 nyan Exp $
*/
/*
* Ported from:
* advansys.c - Linux Host Driver for AdvanSys SCSI Adapters
*
* Copyright (c) 1995-1996 Advanced System Products, Inc.
* All Rights Reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that redistributions of source
* code retain the above copyright notice and this comment without
* modification.
*/
#include <sys/param.h>
#include <sys/kernel.h>
#include <sys/systm.h>
#include <sys/thread2.h>
#include <sys/bus.h>
#include <sys/rman.h>
#include <machine/clock.h>
#include <bus/cam/cam.h>
#include <bus/cam/cam_ccb.h>
#include <bus/cam/cam_sim.h>
#include <bus/cam/cam_xpt_sim.h>
#include <bus/cam/scsi/scsi_all.h>
#include <bus/cam/scsi/scsi_message.h>
#include <bus/cam/scsi/scsi_da.h>
#include <bus/cam/scsi/scsi_cd.h>
#include <vm/vm.h>
#include <vm/vm_param.h>
#include <vm/pmap.h>
#include "advansys.h"
#include "advmcode.h"
struct adv_quirk_entry {
struct scsi_inquiry_pattern inq_pat;
u_int8_t quirks;
#define ADV_QUIRK_FIX_ASYN_XFER_ALWAYS 0x01
#define ADV_QUIRK_FIX_ASYN_XFER 0x02
};
static struct adv_quirk_entry adv_quirk_table[] =
{
{
{ T_CDROM, SIP_MEDIA_REMOVABLE, "HP", "*", "*" },
ADV_QUIRK_FIX_ASYN_XFER_ALWAYS|ADV_QUIRK_FIX_ASYN_XFER
},
{
{ T_CDROM, SIP_MEDIA_REMOVABLE, "NEC", "CD-ROM DRIVE", "*" },
0
},
{
{
T_SEQUENTIAL, SIP_MEDIA_REMOVABLE,
"TANDBERG", " TDC 36", "*"
},
0
},
{
{ T_SEQUENTIAL, SIP_MEDIA_REMOVABLE, "WANGTEK", "*", "*" },
0
},
{
{
T_PROCESSOR, SIP_MEDIA_REMOVABLE|SIP_MEDIA_FIXED,
"*", "*", "*"
},
0
},
{
{
T_SCANNER, SIP_MEDIA_REMOVABLE|SIP_MEDIA_FIXED,
"*", "*", "*"
},
0
},
{
/* Default quirk entry */
{
T_ANY, SIP_MEDIA_REMOVABLE|SIP_MEDIA_FIXED,
/*vendor*/"*", /*product*/"*", /*revision*/"*"
},
ADV_QUIRK_FIX_ASYN_XFER,
}
};
/*
* Allowable periods in ns
*/
static u_int8_t adv_sdtr_period_tbl[] =
{
25,
30,
35,
40,
50,
60,
70,
85
};
static u_int8_t adv_sdtr_period_tbl_ultra[] =
{
12,
19,
25,
32,
38,
44,
50,
57,
63,
69,
75,
82,
88,
94,
100,
107
};
struct ext_msg {
u_int8_t msg_type;
u_int8_t msg_len;
u_int8_t msg_req;
union {
struct {
u_int8_t sdtr_xfer_period;
u_int8_t sdtr_req_ack_offset;
} sdtr;
struct {
u_int8_t wdtr_width;
} wdtr;
struct {
u_int8_t mdp[4];
} mdp;
} u_ext_msg;
u_int8_t res;
};
#define xfer_period u_ext_msg.sdtr.sdtr_xfer_period
#define req_ack_offset u_ext_msg.sdtr.sdtr_req_ack_offset
#define wdtr_width u_ext_msg.wdtr.wdtr_width
#define mdp_b3 u_ext_msg.mdp_b3
#define mdp_b2 u_ext_msg.mdp_b2
#define mdp_b1 u_ext_msg.mdp_b1
#define mdp_b0 u_ext_msg.mdp_b0
/*
* Some of the early PCI adapters have problems with
* async transfers. Instead use an offset of 1.
*/
#define ASYN_SDTR_DATA_FIX_PCI_REV_AB 0x41
/* LRAM routines */
static void adv_read_lram_16_multi(struct adv_softc *adv, u_int16_t s_addr,
u_int16_t *buffer, int count);
static void adv_write_lram_16_multi(struct adv_softc *adv,
u_int16_t s_addr, u_int16_t *buffer,
int count);
static void adv_mset_lram_16(struct adv_softc *adv, u_int16_t s_addr,
u_int16_t set_value, int count);
static u_int32_t adv_msum_lram_16(struct adv_softc *adv, u_int16_t s_addr,
int count);
static int adv_write_and_verify_lram_16(struct adv_softc *adv,
u_int16_t addr, u_int16_t value);
static u_int32_t adv_read_lram_32(struct adv_softc *adv, u_int16_t addr);
static void adv_write_lram_32(struct adv_softc *adv, u_int16_t addr,
u_int32_t value);
static void adv_write_lram_32_multi(struct adv_softc *adv,
u_int16_t s_addr, u_int32_t *buffer,
int count);
/* EEPROM routines */
static u_int16_t adv_read_eeprom_16(struct adv_softc *adv, u_int8_t addr);
static u_int16_t adv_write_eeprom_16(struct adv_softc *adv, u_int8_t addr,
u_int16_t value);
static int adv_write_eeprom_cmd_reg(struct adv_softc *adv,
u_int8_t cmd_reg);
static int adv_set_eeprom_config_once(struct adv_softc *adv,
struct adv_eeprom_config *eeconfig);
/* Initialization */
static u_int32_t adv_load_microcode(struct adv_softc *adv, u_int16_t s_addr,
u_int16_t *mcode_buf, u_int16_t mcode_size);
static void adv_reinit_lram(struct adv_softc *adv);
static void adv_init_lram(struct adv_softc *adv);
static int adv_init_microcode_var(struct adv_softc *adv);
static void adv_init_qlink_var(struct adv_softc *adv);
/* Interrupts */
static void adv_disable_interrupt(struct adv_softc *adv);
static void adv_enable_interrupt(struct adv_softc *adv);
static void adv_toggle_irq_act(struct adv_softc *adv);
/* Chip Control */
static int adv_host_req_chip_halt(struct adv_softc *adv);
static void adv_set_chip_ih(struct adv_softc *adv, u_int16_t ins_code);
#if 0 /* UNUSED */
static u_int8_t adv_get_chip_scsi_ctrl(struct adv_softc *adv);
#endif
/* Queue handling and execution */
static __inline int
adv_sgcount_to_qcount(int sgcount);
static __inline int
adv_sgcount_to_qcount(int sgcount)
{
int n_sg_list_qs;
n_sg_list_qs = ((sgcount - 1) / ADV_SG_LIST_PER_Q);
if (((sgcount - 1) % ADV_SG_LIST_PER_Q) != 0)
n_sg_list_qs++;
return (n_sg_list_qs + 1);
}
static void adv_get_q_info(struct adv_softc *adv, u_int16_t s_addr,
u_int16_t *inbuf, int words);
static u_int adv_get_num_free_queues(struct adv_softc *adv, u_int8_t n_qs);
static u_int8_t adv_alloc_free_queues(struct adv_softc *adv,
u_int8_t free_q_head, u_int8_t n_free_q);
static u_int8_t adv_alloc_free_queue(struct adv_softc *adv,
u_int8_t free_q_head);
static int adv_send_scsi_queue(struct adv_softc *adv,
struct adv_scsi_q *scsiq,
u_int8_t n_q_required);
static void adv_put_ready_sg_list_queue(struct adv_softc *adv,
struct adv_scsi_q *scsiq,
u_int q_no);
static void adv_put_ready_queue(struct adv_softc *adv,
struct adv_scsi_q *scsiq, u_int q_no);
static void adv_put_scsiq(struct adv_softc *adv, u_int16_t s_addr,
u_int16_t *buffer, int words);
/* Messages */
static void adv_handle_extmsg_in(struct adv_softc *adv,
u_int16_t halt_q_addr, u_int8_t q_cntl,
target_bit_vector target_id,
int tid);
static void adv_msgout_sdtr(struct adv_softc *adv, u_int8_t sdtr_period,
u_int8_t sdtr_offset);
static void adv_set_sdtr_reg_at_id(struct adv_softc *adv, int id,
u_int8_t sdtr_data);
/* Exported functions first */
void
advasync(void *callback_arg, u_int32_t code, struct cam_path *path, void *arg)
{
struct adv_softc *adv;
adv = (struct adv_softc *)callback_arg;
switch (code) {
case AC_FOUND_DEVICE:
{
struct ccb_getdev *cgd;
target_bit_vector target_mask;
int num_entries;
caddr_t match;
struct adv_quirk_entry *entry;
struct adv_target_transinfo* tinfo;
cgd = (struct ccb_getdev *)arg;
target_mask = ADV_TID_TO_TARGET_MASK(cgd->ccb_h.target_id);
num_entries = sizeof(adv_quirk_table)/sizeof(*adv_quirk_table);
match = cam_quirkmatch((caddr_t)&cgd->inq_data,
(caddr_t)adv_quirk_table,
num_entries, sizeof(*adv_quirk_table),
scsi_inquiry_match);
if (match == NULL)
panic("advasync: device didn't match wildcard entry!!");
entry = (struct adv_quirk_entry *)match;
if (adv->bug_fix_control & ADV_BUG_FIX_ASYN_USE_SYN) {
if ((entry->quirks & ADV_QUIRK_FIX_ASYN_XFER_ALWAYS)!=0)
adv->fix_asyn_xfer_always |= target_mask;
else
adv->fix_asyn_xfer_always &= ~target_mask;
/*
* We start out life with all bits set and clear them
* after we've determined that the fix isn't necessary.
* It may well be that we've already cleared a target
* before the full inquiry session completes, so don't
* gratuitously set a target bit even if it has this
* quirk. But, if the quirk exonerates a device, clear
* the bit now.
*/
if ((entry->quirks & ADV_QUIRK_FIX_ASYN_XFER) == 0)
adv->fix_asyn_xfer &= ~target_mask;
}
/*
* Reset our sync settings now that we've determined
* what quirks are in effect for the device.
*/
tinfo = &adv->tinfo[cgd->ccb_h.target_id];
adv_set_syncrate(adv, cgd->ccb_h.path,
cgd->ccb_h.target_id,
tinfo->current.period,
tinfo->current.offset,
ADV_TRANS_CUR);
break;
}
case AC_LOST_DEVICE:
{
u_int target_mask;
if (adv->bug_fix_control & ADV_BUG_FIX_ASYN_USE_SYN) {
target_mask = 0x01 << xpt_path_target_id(path);
adv->fix_asyn_xfer |= target_mask;
}
/*
* Revert to async transfers
* for the next device.
*/
adv_set_syncrate(adv, /*path*/NULL,
xpt_path_target_id(path),
/*period*/0,
/*offset*/0,
ADV_TRANS_GOAL|ADV_TRANS_CUR);
}
default:
break;
}
}
void
adv_set_bank(struct adv_softc *adv, u_int8_t bank)
{
u_int8_t control;
/*
* Start out with the bank reset to 0
*/
control = ADV_INB(adv, ADV_CHIP_CTRL)
& (~(ADV_CC_SINGLE_STEP | ADV_CC_TEST
| ADV_CC_DIAG | ADV_CC_SCSI_RESET
| ADV_CC_CHIP_RESET | ADV_CC_BANK_ONE));
if (bank == 1) {
control |= ADV_CC_BANK_ONE;
} else if (bank == 2) {
control |= ADV_CC_DIAG | ADV_CC_BANK_ONE;
}
ADV_OUTB(adv, ADV_CHIP_CTRL, control);
}
u_int8_t
adv_read_lram_8(struct adv_softc *adv, u_int16_t addr)
{
u_int8_t byte_data;
u_int16_t word_data;
/*
* LRAM is accessed on 16bit boundaries.
*/
ADV_OUTW(adv, ADV_LRAM_ADDR, addr & 0xFFFE);
word_data = ADV_INW(adv, ADV_LRAM_DATA);
if (addr & 1) {
#if BYTE_ORDER == BIG_ENDIAN
byte_data = (u_int8_t)(word_data & 0xFF);
#else
byte_data = (u_int8_t)((word_data >> 8) & 0xFF);
#endif
} else {
#if BYTE_ORDER == BIG_ENDIAN
byte_data = (u_int8_t)((word_data >> 8) & 0xFF);
#else
byte_data = (u_int8_t)(word_data & 0xFF);
#endif
}
return (byte_data);
}
void
adv_write_lram_8(struct adv_softc *adv, u_int16_t addr, u_int8_t value)
{
u_int16_t word_data;
word_data = adv_read_lram_16(adv, addr & 0xFFFE);
if (addr & 1) {
word_data &= 0x00FF;
word_data |= (((u_int8_t)value << 8) & 0xFF00);
} else {
word_data &= 0xFF00;
word_data |= ((u_int8_t)value & 0x00FF);
}
adv_write_lram_16(adv, addr & 0xFFFE, word_data);
}
u_int16_t
adv_read_lram_16(struct adv_softc *adv, u_int16_t addr)
{
ADV_OUTW(adv, ADV_LRAM_ADDR, addr);
return (ADV_INW(adv, ADV_LRAM_DATA));
}
void
adv_write_lram_16(struct adv_softc *adv, u_int16_t addr, u_int16_t value)
{
ADV_OUTW(adv, ADV_LRAM_ADDR, addr);
ADV_OUTW(adv, ADV_LRAM_DATA, value);
}
/*
* Determine if there is a board at "iobase" by looking
* for the AdvanSys signatures. Return 1 if a board is
* found, 0 otherwise.
*/
int
adv_find_signature(bus_space_tag_t tag, bus_space_handle_t bsh)
{
u_int16_t signature;
if (bus_space_read_1(tag, bsh, ADV_SIGNATURE_BYTE) == ADV_1000_ID1B) {
signature = bus_space_read_2(tag, bsh, ADV_SIGNATURE_WORD);
if ((signature == ADV_1000_ID0W)
|| (signature == ADV_1000_ID0W_FIX))
return (1);
}
return (0);
}
void
adv_lib_init(struct adv_softc *adv)
{
if ((adv->type & ADV_ULTRA) != 0) {
adv->sdtr_period_tbl = adv_sdtr_period_tbl_ultra;
adv->sdtr_period_tbl_size = sizeof(adv_sdtr_period_tbl_ultra);
} else {
adv->sdtr_period_tbl = adv_sdtr_period_tbl;
adv->sdtr_period_tbl_size = sizeof(adv_sdtr_period_tbl);
}
}
u_int16_t
adv_get_eeprom_config(struct adv_softc *adv, struct
adv_eeprom_config *eeprom_config)
{
u_int16_t sum;
u_int16_t *wbuf;
u_int8_t cfg_beg;
u_int8_t cfg_end;
u_int8_t s_addr;
wbuf = (u_int16_t *)eeprom_config;
sum = 0;
for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) {
*wbuf = adv_read_eeprom_16(adv, s_addr);
sum += *wbuf;
}
if (adv->type & ADV_VL) {
cfg_beg = ADV_EEPROM_CFG_BEG_VL;
cfg_end = ADV_EEPROM_MAX_ADDR_VL;
} else {
cfg_beg = ADV_EEPROM_CFG_BEG;
cfg_end = ADV_EEPROM_MAX_ADDR;
}
for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) {
*wbuf = adv_read_eeprom_16(adv, s_addr);
sum += *wbuf;
#if ADV_DEBUG_EEPROM
kprintf("Addr 0x%x: 0x%04x\n", s_addr, *wbuf);
#endif
}
*wbuf = adv_read_eeprom_16(adv, s_addr);
return (sum);
}
int
adv_set_eeprom_config(struct adv_softc *adv,
struct adv_eeprom_config *eeprom_config)
{
int retry;
retry = 0;
while (1) {
if (adv_set_eeprom_config_once(adv, eeprom_config) == 0) {
break;
}
if (++retry > ADV_EEPROM_MAX_RETRY) {
break;
}
}
return (retry > ADV_EEPROM_MAX_RETRY);
}
int
adv_reset_chip(struct adv_softc *adv, int reset_bus)
{
adv_stop_chip(adv);
ADV_OUTB(adv, ADV_CHIP_CTRL, ADV_CC_CHIP_RESET | ADV_CC_HALT
| (reset_bus ? ADV_CC_SCSI_RESET : 0));
DELAY(60);
adv_set_chip_ih(adv, ADV_INS_RFLAG_WTM);
adv_set_chip_ih(adv, ADV_INS_HALT);
if (reset_bus)
ADV_OUTB(adv, ADV_CHIP_CTRL, ADV_CC_CHIP_RESET | ADV_CC_HALT);
ADV_OUTB(adv, ADV_CHIP_CTRL, ADV_CC_HALT);
if (reset_bus)
DELAY(200 * 1000);
ADV_OUTW(adv, ADV_CHIP_STATUS, ADV_CIW_CLR_SCSI_RESET_INT);
ADV_OUTW(adv, ADV_CHIP_STATUS, 0);
return (adv_is_chip_halted(adv));
}
int
adv_test_external_lram(struct adv_softc* adv)
{
u_int16_t q_addr;
u_int16_t saved_value;
int success;
success = 0;
q_addr = ADV_QNO_TO_QADDR(241);
saved_value = adv_read_lram_16(adv, q_addr);
if (adv_write_and_verify_lram_16(adv, q_addr, 0x55AA) == 0) {
success = 1;
adv_write_lram_16(adv, q_addr, saved_value);
}
return (success);
}
int
adv_init_lram_and_mcode(struct adv_softc *adv)
{
u_int32_t retval;
adv_disable_interrupt(adv);
adv_init_lram(adv);
retval = adv_load_microcode(adv, 0, (u_int16_t *)adv_mcode,
adv_mcode_size);
if (retval != adv_mcode_chksum) {
kprintf("adv%d: Microcode download failed checksum!\n",
adv->unit);
return (1);
}
if (adv_init_microcode_var(adv) != 0)
return (1);
adv_enable_interrupt(adv);
return (0);
}
u_int8_t
adv_get_chip_irq(struct adv_softc *adv)
{
u_int16_t cfg_lsw;
u_int8_t chip_irq;
cfg_lsw = ADV_INW(adv, ADV_CONFIG_LSW);
if ((adv->type & ADV_VL) != 0) {
chip_irq = (u_int8_t)(((cfg_lsw >> 2) & 0x07));
if ((chip_irq == 0) ||
(chip_irq == 4) ||
(chip_irq == 7)) {
return (0);
}
return (chip_irq + (ADV_MIN_IRQ_NO - 1));
}
chip_irq = (u_int8_t)(((cfg_lsw >> 2) & 0x03));
if (chip_irq == 3)
chip_irq += 2;
return (chip_irq + ADV_MIN_IRQ_NO);
}
u_int8_t
adv_set_chip_irq(struct adv_softc *adv, u_int8_t irq_no)
{
u_int16_t cfg_lsw;
if ((adv->type & ADV_VL) != 0) {
if (irq_no != 0) {
if ((irq_no < ADV_MIN_IRQ_NO)
|| (irq_no > ADV_MAX_IRQ_NO)) {
irq_no = 0;
} else {
irq_no -= ADV_MIN_IRQ_NO - 1;
}
}
cfg_lsw = ADV_INW(adv, ADV_CONFIG_LSW) & 0xFFE3;
cfg_lsw |= 0x0010;
ADV_OUTW(adv, ADV_CONFIG_LSW, cfg_lsw);
adv_toggle_irq_act(adv);
cfg_lsw = ADV_INW(adv, ADV_CONFIG_LSW) & 0xFFE0;
cfg_lsw |= (irq_no & 0x07) << 2;
ADV_OUTW(adv, ADV_CONFIG_LSW, cfg_lsw);
adv_toggle_irq_act(adv);
} else if ((adv->type & ADV_ISA) != 0) {
if (irq_no == 15)
irq_no -= 2;
irq_no -= ADV_MIN_IRQ_NO;
cfg_lsw = ADV_INW(adv, ADV_CONFIG_LSW) & 0xFFF3;
cfg_lsw |= (irq_no & 0x03) << 2;
ADV_OUTW(adv, ADV_CONFIG_LSW, cfg_lsw);
}
return (adv_get_chip_irq(adv));
}
void
adv_set_chip_scsiid(struct adv_softc *adv, int new_id)
{
u_int16_t cfg_lsw;
cfg_lsw = ADV_INW(adv, ADV_CONFIG_LSW);
if (ADV_CONFIG_SCSIID(cfg_lsw) == new_id)
return;
cfg_lsw &= ~ADV_CFG_LSW_SCSIID;
cfg_lsw |= (new_id & ADV_MAX_TID) << ADV_CFG_LSW_SCSIID_SHIFT;
ADV_OUTW(adv, ADV_CONFIG_LSW, cfg_lsw);
}
int
adv_execute_scsi_queue(struct adv_softc *adv, struct adv_scsi_q *scsiq,
u_int32_t datalen)
{
struct adv_target_transinfo* tinfo;
u_int32_t *p_data_addr;
u_int32_t *p_data_bcount;
int disable_syn_offset_one_fix;
int retval;
u_int n_q_required;
u_int32_t addr;
u_int8_t sg_entry_cnt;
u_int8_t target_ix;
u_int8_t sg_entry_cnt_minus_one;
u_int8_t tid_no;
scsiq->q1.q_no = 0;
retval = 1; /* Default to error case */
target_ix = scsiq->q2.target_ix;
tid_no = ADV_TIX_TO_TID(target_ix);
tinfo = &adv->tinfo[tid_no];
if (scsiq->cdbptr[0] == REQUEST_SENSE) {
/* Renegotiate if appropriate. */
adv_set_syncrate(adv, /*struct cam_path */NULL,
tid_no, /*period*/0, /*offset*/0,
ADV_TRANS_CUR);
if (tinfo->current.period != tinfo->goal.period) {
adv_msgout_sdtr(adv, tinfo->goal.period,
tinfo->goal.offset);
scsiq->q1.cntl |= (QC_MSG_OUT | QC_URGENT);
}
}
if ((scsiq->q1.cntl & QC_SG_HEAD) != 0) {
sg_entry_cnt = scsiq->sg_head->entry_cnt;
sg_entry_cnt_minus_one = sg_entry_cnt - 1;
#ifdef DIAGNOSTIC
if (sg_entry_cnt <= 1)
panic("adv_execute_scsi_queue: Queue "
"with QC_SG_HEAD set but %d segs.", sg_entry_cnt);
if (sg_entry_cnt > ADV_MAX_SG_LIST)
panic("adv_execute_scsi_queue: "
"Queue with too many segs.");
if ((adv->type & (ADV_ISA | ADV_VL | ADV_EISA)) != 0) {
int i;
for (i = 0; i < sg_entry_cnt_minus_one; i++) {
addr = scsiq->sg_head->sg_list[i].addr +
scsiq->sg_head->sg_list[i].bytes;
if ((addr & 0x0003) != 0)
panic("adv_execute_scsi_queue: SG "
"with odd address or byte count");
}
}
#endif
p_data_addr =
&scsiq->sg_head->sg_list[sg_entry_cnt_minus_one].addr;
p_data_bcount =
&scsiq->sg_head->sg_list[sg_entry_cnt_minus_one].bytes;
n_q_required = adv_sgcount_to_qcount(sg_entry_cnt);
scsiq->sg_head->queue_cnt = n_q_required - 1;
} else {
p_data_addr = &scsiq->q1.data_addr;
p_data_bcount = &scsiq->q1.data_cnt;
n_q_required = 1;
}
disable_syn_offset_one_fix = FALSE;
if ((adv->fix_asyn_xfer & scsiq->q1.target_id) != 0
&& (adv->fix_asyn_xfer_always & scsiq->q1.target_id) == 0) {
if (datalen != 0) {
if (datalen < 512) {
disable_syn_offset_one_fix = TRUE;
} else {
if (scsiq->cdbptr[0] == INQUIRY
|| scsiq->cdbptr[0] == REQUEST_SENSE
|| scsiq->cdbptr[0] == READ_CAPACITY
|| scsiq->cdbptr[0] == MODE_SELECT_6
|| scsiq->cdbptr[0] == MODE_SENSE_6
|| scsiq->cdbptr[0] == MODE_SENSE_10
|| scsiq->cdbptr[0] == MODE_SELECT_10
|| scsiq->cdbptr[0] == READ_TOC) {
disable_syn_offset_one_fix = TRUE;
}
}
}
}
if (disable_syn_offset_one_fix) {
scsiq->q2.tag_code &=
~(MSG_SIMPLE_Q_TAG|MSG_HEAD_OF_Q_TAG|MSG_ORDERED_Q_TAG);
scsiq->q2.tag_code |= (ADV_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX
| ADV_TAG_FLAG_DISABLE_DISCONNECT);
}
if ((adv->bug_fix_control & ADV_BUG_FIX_IF_NOT_DWB) != 0
&& (scsiq->cdbptr[0] == READ_10 || scsiq->cdbptr[0] == READ_6)) {
u_int8_t extra_bytes;
addr = *p_data_addr + *p_data_bcount;
extra_bytes = addr & 0x0003;
if (extra_bytes != 0
&& ((scsiq->q1.cntl & QC_SG_HEAD) != 0
|| (scsiq->q1.data_cnt & 0x01FF) == 0)) {
scsiq->q2.tag_code |= ADV_TAG_FLAG_EXTRA_BYTES;
scsiq->q1.extra_bytes = extra_bytes;
*p_data_bcount -= extra_bytes;
}
}
if ((adv_get_num_free_queues(adv, n_q_required) >= n_q_required)
|| ((scsiq->q1.cntl & QC_URGENT) != 0))
retval = adv_send_scsi_queue(adv, scsiq, n_q_required);
return (retval);
}
u_int8_t
adv_copy_lram_doneq(struct adv_softc *adv, u_int16_t q_addr,
struct adv_q_done_info *scsiq, u_int32_t max_dma_count)
{
u_int16_t val;
u_int8_t sg_queue_cnt;
adv_get_q_info(adv, q_addr + ADV_SCSIQ_DONE_INFO_BEG,
(u_int16_t *)scsiq,
(sizeof(scsiq->d2) + sizeof(scsiq->d3)) / 2);
#if BYTE_ORDER == BIG_ENDIAN
adv_adj_endian_qdone_info(scsiq);
#endif
val = adv_read_lram_16(adv, q_addr + ADV_SCSIQ_B_STATUS);
scsiq->q_status = val & 0xFF;
scsiq->q_no = (val >> 8) & 0XFF;
val = adv_read_lram_16(adv, q_addr + ADV_SCSIQ_B_CNTL);
scsiq->cntl = val & 0xFF;
sg_queue_cnt = (val >> 8) & 0xFF;
val = adv_read_lram_16(adv,q_addr + ADV_SCSIQ_B_SENSE_LEN);
scsiq->sense_len = val & 0xFF;
scsiq->extra_bytes = (val >> 8) & 0xFF;
/*
* Due to a bug in accessing LRAM on the 940UA, the residual
* is split into separate high and low 16bit quantities.
*/
scsiq->remain_bytes =
adv_read_lram_16(adv, q_addr + ADV_SCSIQ_DW_REMAIN_XFER_CNT);
scsiq->remain_bytes |=
adv_read_lram_16(adv, q_addr + ADV_SCSIQ_W_ALT_DC1) << 16;
/*
* XXX Is this just a safeguard or will the counter really
* have bogus upper bits?
*/
scsiq->remain_bytes &= max_dma_count;
return (sg_queue_cnt);
}
int
adv_start_chip(struct adv_softc *adv)
{
ADV_OUTB(adv, ADV_CHIP_CTRL, 0);
if ((ADV_INW(adv, ADV_CHIP_STATUS) & ADV_CSW_HALTED) != 0)
return (0);
return (1);
}
int
adv_stop_execution(struct adv_softc *adv)
{
int count;
count = 0;
if (adv_read_lram_8(adv, ADV_STOP_CODE_B) == 0) {
adv_write_lram_8(adv, ADV_STOP_CODE_B,
ADV_STOP_REQ_RISC_STOP);
do {
if (adv_read_lram_8(adv, ADV_STOP_CODE_B) &
ADV_STOP_ACK_RISC_STOP) {
return (1);
}
DELAY(1000);
} while (count++ < 20);
}
return (0);
}
int
adv_is_chip_halted(struct adv_softc *adv)
{
if ((ADV_INW(adv, ADV_CHIP_STATUS) & ADV_CSW_HALTED) != 0) {
if ((ADV_INB(adv, ADV_CHIP_CTRL) & ADV_CC_HALT) != 0) {
return (1);
}
}
return (0);
}
/*
* XXX The numeric constants and the loops in this routine
* need to be documented.
*/
void
adv_ack_interrupt(struct adv_softc *adv)
{
u_int8_t host_flag;
u_int8_t risc_flag;
int loop;
loop = 0;
do {
risc_flag = adv_read_lram_8(adv, ADVV_RISC_FLAG_B);
if (loop++ > 0x7FFF) {
break;
}
} while ((risc_flag & ADV_RISC_FLAG_GEN_INT) != 0);
host_flag = adv_read_lram_8(adv, ADVV_HOST_FLAG_B);
adv_write_lram_8(adv, ADVV_HOST_FLAG_B,
host_flag | ADV_HOST_FLAG_ACK_INT);
ADV_OUTW(adv, ADV_CHIP_STATUS, ADV_CIW_INT_ACK);
loop = 0;
while (ADV_INW(adv, ADV_CHIP_STATUS) & ADV_CSW_INT_PENDING) {
ADV_OUTW(adv, ADV_CHIP_STATUS, ADV_CIW_INT_ACK);
if (loop++ > 3) {
break;
}
}
adv_write_lram_8(adv, ADVV_HOST_FLAG_B, host_flag);
}
/*
* Handle all conditions that may halt the chip waiting
* for us to intervene.
*/
void
adv_isr_chip_halted(struct adv_softc *adv)
{
u_int16_t int_halt_code;
u_int16_t halt_q_addr;
target_bit_vector target_mask;
target_bit_vector scsi_busy;
u_int8_t halt_qp;
u_int8_t target_ix;
u_int8_t q_cntl;
u_int8_t tid_no;
int_halt_code = adv_read_lram_16(adv, ADVV_HALTCODE_W);
halt_qp = adv_read_lram_8(adv, ADVV_CURCDB_B);
halt_q_addr = ADV_QNO_TO_QADDR(halt_qp);
target_ix = adv_read_lram_8(adv, halt_q_addr + ADV_SCSIQ_B_TARGET_IX);
q_cntl = adv_read_lram_8(adv, halt_q_addr + ADV_SCSIQ_B_CNTL);
tid_no = ADV_TIX_TO_TID(target_ix);
target_mask = ADV_TID_TO_TARGET_MASK(tid_no);
if (int_halt_code == ADV_HALT_DISABLE_ASYN_USE_SYN_FIX) {
/*
* Temporarily disable the async fix by removing
* this target from the list of affected targets,
* setting our async rate, and then putting us
* back into the mask.
*/
adv->fix_asyn_xfer &= ~target_mask;
adv_set_syncrate(adv, /*struct cam_path */NULL,
tid_no, /*period*/0, /*offset*/0,
ADV_TRANS_ACTIVE);
adv->fix_asyn_xfer |= target_mask;
} else if (int_halt_code == ADV_HALT_ENABLE_ASYN_USE_SYN_FIX) {
adv_set_syncrate(adv, /*struct cam_path */NULL,
tid_no, /*period*/0, /*offset*/0,
ADV_TRANS_ACTIVE);
} else if (int_halt_code == ADV_HALT_EXTMSG_IN) {
adv_handle_extmsg_in(adv, halt_q_addr, q_cntl,
target_mask, tid_no);
} else if (int_halt_code == ADV_HALT_CHK_CONDITION) {
struct adv_target_transinfo* tinfo;
union ccb *ccb;
u_int32_t cinfo_index;
u_int8_t tag_code;
u_int8_t q_status;
tinfo = &adv->tinfo[tid_no];
q_cntl |= QC_REQ_SENSE;
/* Renegotiate if appropriate. */
adv_set_syncrate(adv, /*struct cam_path */NULL,
tid_no, /*period*/0, /*offset*/0,
ADV_TRANS_CUR);
if (tinfo->current.period != tinfo->goal.period) {
adv_msgout_sdtr(adv, tinfo->goal.period,
tinfo->goal.offset);
q_cntl |= QC_MSG_OUT;
}
adv_write_lram_8(adv, halt_q_addr + ADV_SCSIQ_B_CNTL, q_cntl);
/* Don't tag request sense commands */
tag_code = adv_read_lram_8(adv,
halt_q_addr + ADV_SCSIQ_B_TAG_CODE);
tag_code &=
~(MSG_SIMPLE_Q_TAG|MSG_HEAD_OF_Q_TAG|MSG_ORDERED_Q_TAG);
if ((adv->fix_asyn_xfer & target_mask) != 0
&& (adv->fix_asyn_xfer_always & target_mask) == 0) {
tag_code |= (ADV_TAG_FLAG_DISABLE_DISCONNECT
| ADV_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX);
}
adv_write_lram_8(adv, halt_q_addr + ADV_SCSIQ_B_TAG_CODE,
tag_code);
q_status = adv_read_lram_8(adv,
halt_q_addr + ADV_SCSIQ_B_STATUS);
q_status |= (QS_READY | QS_BUSY);
adv_write_lram_8(adv, halt_q_addr + ADV_SCSIQ_B_STATUS,
q_status);