staging: vc04_services: Fix bulk cache maintenance #1987
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vchiq_arm supports transfers less than one page and at arbitrary alignment, using the dma-mapping API to perform its cache maintenance (even though the VPU drives the DMA hardware). Read (DMA_FROM_DEVICE) operations use cache invalidation for speed, falling back to clean+invalidate on partial cache lines, with writes (DMA_TO_DEVICE) using flushes. If a read transfer has ends which aren't page-aligned, performing cache maintenance as if they were whole pages can lead to memory corruption since the partial cache lines at the ends (and any cache lines before or after the transfer area) will be invalidated. This bug was masked until the disabling of the cache flush in flush_dcache_page(). Honouring the requested transfer start- and end-points prevents the corruption. See: raspberrypi#1977 Signed-off-by: Phil Elwell <phil@raspberrypi.org>
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Tested downstream builds on B+, Pi2 and Pi3. |
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Looks good. vchiq_test is happy for me and kodi still runs. |
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My bulk test is not happy. "vchiq_test -b 16 1" |
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I can't reproduce that. Can you replace the WARN_ON with a WARN that logs k, dma_buffers and len? For bonus marks, dump out the whole scatterlist. |
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Never mind - I've got one. |
pelwell
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create_pagelist uses a number of WARNs to sanity-check check the input user pages, verifying that only the first and last entries in the array are not integral pages. These WARNs use the output array index when it should be input array index. Although the difference is only significant in one instance, change all the indices for consistency. See: raspberrypi#1987 Signed-off-by: Phil Elwell <phil@raspberrypi.org>
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Found it - see #1990. |
popcornmix
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that referenced
this pull request
May 4, 2017
create_pagelist uses a number of WARNs to sanity-check check the input user pages, verifying that only the first and last entries in the array are not integral pages. These WARNs use the output array index when it should be input array index. Although the difference is only significant in one instance, change all the indices for consistency. See: #1987 Signed-off-by: Phil Elwell <phil@raspberrypi.org>
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vchiq_arm supports transfers less than one page and at arbitrary
alignment, using the dma-mapping API to perform its cache maintenance
(even though the VPU drives the DMA hardware). Read (DMA_FROM_DEVICE)
operations use cache invalidation for speed, falling back to
clean+invalidate on partial cache lines, with writes (DMA_TO_DEVICE)
using flushes.
If a read transfer has ends which aren't page-aligned, performing cache
maintenance as if they were whole pages can lead to memory corruption
since the partial cache lines at the ends (and any cache lines before or
after the transfer area) will be invalidated. This bug was masked until
the disabling of the cache flush in flush_dcache_page().
Honouring the requested transfer start- and end-points prevents the
corruption.
See: #1977
Signed-off-by: Phil Elwell phil@raspberrypi.org