DSI0 colour swap fixes #6094
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DSI0 colour swap fixes #6094
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The autodetection of resolution/timing by the TC358762 can lead to the display being shifted by a pixel or two. Program the TC358762 with the requested mode timing so that it can reproduce it accurately. Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
Reverts 8a4b2fc ("drm/bridge: tc358762: Split register programming from pre-enable to enable") as we want the config commands sent before video starts. Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
The initialisation sequence differs slightly from the documentation in that the clocks are meant to be running before resets and similar. Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
vc4_dsi_bridge_disable wasn't resetting things during shutdown, so add that in. Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
The block must be enabled for the FIFO resets to be actioned, so ensure this is the case. Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
DSI0 is misbehaving and needs to action things on vblank to work around it. Add a new hook to call across during vblank. Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
The pixel to byte FIFO appears to not always reset correctly, which can lead to colour errors and/or horizontal shifts. Reset on every vblank to work around the issue. Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
DSI0 can take the clock from either PLLA or PLLD. PLLA is the default muxing, but PLLD is considered the more stable. Switch to using PLLD. Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
PLLD is considered more stable than PLLA as it doesn't get varied. The clock muxing has been updated to driver DSI0 from PLLD, so update DT to match. Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
The 7inch panel is one line off the screen both horizontally and vertically. Alter the panel mode to correct this. Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
The Toshiba bridge is very fussy and doesn't like the CM3 output when being told to produce a 27.777MHz pixel clock, which is an almost perfect match to the DSI link integer divider. Increasing to 30MHz will switch the DSI link from 333MHz to 400MHz and makes the bridge happy with the same video timing as works on Pi4. (Pi4 will be using a link frequency of 375MHz due to a 3GHz parent PLL). Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
The TC358762 bridge and panel decodes the mode differently on DSI0 to DSI1 for no obvious reason, and results in a shift off the screen. Whilst it would be possible to change the compatible used for the panel, that then messes up Pi5. As it appears to be restricted to vc4 DSI0, fix up the mode in vc4_dsi. Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
Adds a shutdown function to turn off the backlight, bridge, and touch controller on shutdown. Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
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This seems to fix things for me (with an "old" 7inch Touch Display) for "DISPLAY" on Pi 4 and for "CAM/DISP 1" on a Pi 5, but still not working for "CAM/DISP 0" on a Pi 5? |
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Tested on lurch's setup, and it is his specific 7" display that doesn't like DSI0 on his or my Pi5. My display is happy on both Pi5s. aBUGSworstnightmare-rpi has confirmed on #4946 that DSI0 is working with his TI SN65DSI83 LVDS bridge setup too. I think I'm happy with that. Dropping the draft tag. |
popcornmix
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kernel: DSI0 colour swap fixes See: raspberrypi/linux#6094 kernel: overlays: Add overlay for the Pineboards Hat Ai! See: raspberrypi/linux#6126 kernel: drm: rp1: dpi: Add support for MEDIA_BUS_FMT_RGB565_1X24_CPADHI See: raspberrypi/linux#6132
popcornmix
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kernel: DSI0 colour swap fixes See: raspberrypi/linux#6094 kernel: overlays: Add overlay for the Pineboards Hat Ai! See: raspberrypi/linux#6126 kernel: drm: rp1: dpi: Add support for MEDIA_BUS_FMT_RGB565_1X24_CPADHI See: raspberrypi/linux#6132
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Patches so far trying to make DSI0 behave.