rp1-dsi: Switch to PLL_SYS source for DPI when 8*lanes > bpp #6157
Conversation
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Define two new RP1 clocks, representing the MIPI DSI byteclock sources for the dividers used to generate MIPI[01] DPI pixel clocks. (Previously they were represented by "fake" fixed clocks sources). Signed-off-by: Nick Hollinghurst <nick.hollinghurst@raspberrypi.com>
Add a new class of clocks to RP1 to represent clock sources whose frequency changes at run-time as a side-effect of some other driver. Specifically this is for the two MIPI DSI byte-clock sources. Signed-off-by: Nick Hollinghurst <nick.hollinghurst@raspberrypi.com>
Remove the "dummy" 72MHz fixed clock sources and associate DSI driver with the new "variable" clock sources now defined in RP1 clocks. Also add PLLSYS clock to DSI, which it will need as an alternative clock source in those cases where DPI pixclock > DSI byteclock. Signed-off-by: Nick Hollinghurst <nick.hollinghurst@raspberrypi.com>
To support 4 lanes, re-parent DPI clock source between DSI byteclock (using the new "variable sources" defined in clk-rp1) and PLL_SYS. This is to cover cases in which byteclock < pixclock <= 200MHz. Tidying: All frequencies now in Hz (not kHz), where DSI speed is now represented by byteclock to simplify arithmetic. Clamp DPI and byte clocks to their legal ranges; fix up HSTX timeout to avoid an unsafe assumption that it would return to LP state for every scanline. Because of RP1's clock topology, the ratio between DSI and DPI clocks may not be exact with 3 or 4 lanes, leading to slightly irregular timings each time DSI switches between HS and LP states. Tweak to inhibit LP during Horizontal BP when sync pulses were requested. Signed-off-by: Nick Hollinghurst <nick.hollinghurst@raspberrypi.com>
This was referenced May 10, 2024
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.
This suggestion is invalid because no changes were made to the code.
Suggestions cannot be applied while the pull request is closed.
Suggestions cannot be applied while viewing a subset of changes.
Only one suggestion per line can be applied in a batch.
Add this suggestion to a batch that can be applied as a single commit.
Applying suggestions on deleted lines is not supported.
You must change the existing code in this line in order to create a valid suggestion.
Outdated suggestions cannot be applied.
This suggestion has been applied or marked resolved.
Suggestions cannot be applied from pending reviews.
Suggestions cannot be applied on multi-line comments.
Suggestions cannot be applied while the pull request is queued to merge.
Suggestion cannot be applied right now. Please check back later.
Replaces #6136 after rebase to rpi-6.6.y and with the changes grouped into what I hope is a sensible order.
This ought in principle to fix the clock rate bug with 4-lane DSI on RP1. It does not break the (single-lane) Raspberry Pi 7" Display.
However, I still cannot get a picture (or even a backlight) out of LT070ME05000.