bcm2708_fb: Add ARCH_BCM2835 support #970
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Add Device Tree support. Pass the device to dma_alloc_coherent() in order to get the correct bus address on ARCH_BCM2835. Use the new DMA legacy API header file. Including <mach/platform.h> is not necessary. Signed-off-by: Noralf Trønnes <noralf@tronnes.org>
This header file can be removed since there are no more users. Signed-off-by: Noralf Trønnes <noralf@tronnes.org>
Add bcm2708-fb to Device Tree and don't add the platform device when booting in DT mode. Signed-off-by: Noralf Trønnes <noralf@tronnes.org>
There exists a tiny MMU, configurable only by the VC (running the closed firmware), which maps from the ARM's physical addresses to bus addresses. These bus addresses determine the caching behavior in the VC's L1/L2 (note: separate from the ARM's L1/L2) according to the top 2 bits. The bits in the bus address mean: From the VideoCore processor: 0x0... L1 and L2 cache allocating and coherent 0x4... L1 non-allocating, but coherent. L2 allocating and coherent 0x8... L1 non-allocating, but coherent. L2 non-allocating, but coherent 0xc... SDRAM alias. Cache is bypassed. Not L1 or L2 allocating or coherent From the GPU peripherals (note: all peripherals bypass the L1 cache. The ARM will see this view once through the VC MMU): 0x0... Do not use 0x4... L1 non-allocating, and incoherent. L2 allocating and coherent. 0x8... L1 non-allocating, and incoherent. L2 non-allocating, but coherent 0xc... SDRAM alias. Cache is bypassed. Not L1 or L2 allocating or coherent The 2835 firmware always configures the MMU to turn ARM physical addresses with 0x0 top bits to 0x4, meaning present in L2 but incoherent with L1. However, any bus addresses we were generating in the kernel to be passed to a device had 0x0 bits. That would be a reserved (possibly totally incoherent) value if sent to a GPU peripheral like USB, or L1 allocating if sent to the VC (like a firmware property request). By setting dma-ranges, all of the devices below it get a dev->dma_pfn_offset, so that dma_alloc_coherent() and friends return addresses with 0x4 bits and avoid cache incoherency. This matches the behavior in the downstream 2708 kernel (see BUS_OFFSET in arch/arm/mach-bcm2708/include/mach/memory.h). Signed-off-by: Eric Anholt <eric@anholt.net> Tested-by: Noralf Trønnes <noralf@tronnes.org> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Cc: popcornmix@gmail.com
Add framebuffer device to Device Tree. Signed-off-by: Noralf Trønnes <noralf@tronnes.org>
Enable the bcm2708 framebuffer driver. Disable the simple framebuffer driver, which matches the device handed over by u-boot. Signed-off-by: Noralf Trønnes <noralf@tronnes.org>
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Looks okay to me. @pelwell ? |
pelwell
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May 19, 2015
bcm2708_fb: Add ARCH_BCM2835 support
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Just a footnote: we should now consider Compute Module when making changes to the core devices. I missed enabling the MMC interface on CMs, and this change should probably have enabled the FB there as well. I've pushed patches correcting both of those. |
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Thanks, I will keep that in mind. |
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Use bcm2708_fb on ARCH_BCM2835 instead of SIMPLE_FB.
Add DT node on MACH_BCM270x.
Remove mach/dma.h which is not needed anymore.
Tested on Pi1 and Pi2 regular kernel with and without DT + ARCH_BCM2835.