Adding files to the repo.

BoardDisplay.vhd

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+----------------------------------------------------------------------------------
+--Code by: Zachary Rauen
+--Date: 10/6/14
+--Last Modified: 10/16/14
+--
+--Description: This is a 7 segment display that takes in
+-- a 16 bit number and displays it across 4 7 segment displays
+--
+--Version: 2.3
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity BoardDisplay is
+    Generic (RefreshRate : integer := 1000;
+             ClockSpeed : integer := 100000000);
+    Port ( ClockState : in std_logic;
+           Data : in std_logic_vector(15 downto 0);
+           DisplayVector : out std_logic_vector(7 downto 0);
+           SegmentVector : out std_logic_vector(7 downto 0));
+end BoardDisplay;
+
+architecture Behavioral of BoardDisplay is
+
+
+signal vectorSection : std_logic_vector(3 downto 0);
+signal segCnt : integer := 0;
+signal segCntMax : integer := 3;
+signal dispCarry : std_logic_vector(7 downto 0);
+signal SegmentEnable : std_logic;
+signal clkEnableMax : integer := ClockSpeed/RefreshRate;
+signal clkEnCnt : integer := 0;
+
+begin
+
+
+Refresh: process(ClockState)
+begin
+if rising_edge(ClockState) then
+    if clkEnCnt = clkEnableMax then
+        SegmentEnable <= '1';
+        clkEnCnt <= 0;
+    else
+        clkEnCnt<=clkEnCnt+1;
+        SegmentEnable <= '0';
+    end if;
+end if;
+if rising_edge(ClockState) AND SegmentEnable = '1' then
+    if segCnt = segCntMax then
+        segCnt <= 0;
+    else
+        segCnt <= segCnt + 1;
+    end if;
+end if;
+end process Refresh;
+
+Display: process(ClockState,Data)
+begin
+
+case segCnt is
+    when 0 => 
+    SegmentVector <="11111110";
+    vectorSection <=Data(3 downto 0);
+    when 1 =>
+    SegmentVector <="11111101";
+    vectorSection <=Data(7 downto 4);
+    when 2 =>
+    SegmentVector <="11111011";
+    vectorSection <=Data(11 downto 8);
+    when 3 =>
+    SegmentVector <="11110111";
+    vectorSection <=Data(15 downto 12);
+    when others =>
+    SegmentVector <="11111111";
+    vectorSection <="1111";
+end case;
+
+end process Display;
+with vectorSection select dispCarry <=
+    "11111100" when "0000",
+    "01100000" when "0001",
+    "11011010" when "0010",
+    "11110010" when "0011",
+    "01100110" when "0100",
+    "10110110" when "0101",
+    "10111110" when "0110",
+    "11100000" when "0111",
+    "11111110" when "1000",
+    "11110110" when "1001",
+    "11101110" when "1010",
+    "00111110" when "1011",
+    "10011100" when "1100",
+    "01111010" when "1101",
+    "10011110" when "1110",
+    "10001110" when "1111";
+
+DisplayVector<= NOT dispCarry;
+
+end Behavioral;
+
+
+
+

SPI_display.vhd

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+----------------------------------------------------------------------------------
+--Code by: Zachary Rauen
+--Date: 10/30/14
+--Last Modified: 11/2/14
+--
+--Description: This takes in 16 bit data and displays them on an external display
+-- using GPIO and SPI communication.
+--
+--Version: 1.1
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity SPI_display is
+Generic (constant BoardClockSpeed : integer := 100000000;
+         constant SCKSpeed : integer := 250000);
+    Port ( BoardClock : in STD_LOGIC;
+           Data : in STD_LOGIC_VECTOR (15 downto 0);
+           SCK : out STD_LOGIC;
+           SS : out STD_LOGIC;
+           MOSI : out STD_LOGIC
+           );
+end SPI_display;
+
+architecture Behavioral of SPI_display is
+
+signal clkMax : integer := (BoardClockSpeed/SCKSpeed)-1;
+signal clkCnt : integer := 0;
+signal StateClock : std_logic :='0';
+type state_type is (state0,state1,state2,state3,state4,state5,state6,state7,state8,state9,
+state10,state11,state12,state13,state14,state15,state16,state17,state18);
+signal currentState : state_type :=state0;
+signal nextState : state_type;
+signal dataSection : std_logic_vector(7 downto 0);
+signal byteChoice: integer :=0;
+signal byteMax: integer :=8;
+begin
+
+ClkEnable : process(BoardClock)
+begin
+if rising_edge(BoardClock) then
+    if clkCnt = clkMax then
+        StateClock <= '1';
+        clkCnt <= 0;
+    else
+        clkCnt<=clkCnt+1;
+        StateClock <= '0';
+    end if;
+end if;
+end process ClkEnable;
+
+StateChange: process (BoardClock,StateClock)
+begin
+if (rising_edge(BoardClock) and StateClock='1') then 
+if currentState = state18 then
+    if byteChoice = byteMax then
+    byteChoice <= byteChoice-3;
+    else
+    byteChoice<=byteChoice+1;
+    end if;
+end if;
+    currentState <= nextState;
+end if;
+
+end process StateChange;
+
+States: process(currentState)
+begin
+case currentState is
+    when state0=>
+        SCK<='0';
+        SS<='1';
+        MOSI<='Z';
+        nextState<=state1;
+    when state1=>
+        SCK<='0';
+        SS<='0';
+        MOSI<=dataSection(7);
+        nextState<=state2;        
+    when state2=>
+        SCK<='1';
+        SS<='0';
+        MOSI<=dataSection(7);
+        nextState<=state3;  
+    when state3=>
+       SCK<='0';
+       SS<='0';
+       MOSI<=dataSection(6);
+       nextState<=state4;  
+    when state4=>
+        SCK<='1';
+        SS<='0';
+        MOSI<=dataSection(6);
+        nextState<=state5;  
+    when state5=>
+        SCK<='0';
+        SS<='0';
+        MOSI<=dataSection(5);
+        nextState<=state6;
+    when state6=>
+        SCK<='1';
+        SS<='0';
+        MOSI<=dataSection(5);
+        nextState<=state7;
+    when state7=>
+        SCK<='0';
+        SS<='0';
+        MOSI<=dataSection(4);
+        nextState<=state8;
+    when state8=>
+        SCK<='1';
+        SS<='0';
+        MOSI<=dataSection(4);
+        nextState<=state9;
+    when state9=>
+        SCK<='0';
+        SS<='0';
+        MOSI<=dataSection(3);
+        nextState<=state10;
+    when state10=>
+        SCK<='1';
+        SS<='0';
+        MOSI<=dataSection(3);
+        nextState<=state11;
+    when state11=>
+        SCK<='0';
+        SS<='0';
+        MOSI<=dataSection(2);
+        nextState<=state12;
+    when state12=>
+        SCK<='1';
+        SS<='0';
+        MOSI<=dataSection(2);
+        nextState<=state13;
+    when state13=>
+        SCK<='0';
+        SS<='0';
+        MOSI<=dataSection(1);
+        nextState<=state14;
+    when state14=>
+        SCK<='1';
+        SS<='0';
+        MOSI<=dataSection(1);
+        nextState<=state15;
+    when state15=>
+        SCK<='0';
+        SS<='0';
+        MOSI<=dataSection(0);
+        nextState<=state16;
+    when state16=>
+        SCK<='1';
+        SS<='0';
+        MOSI<=dataSection(0);
+        nextState<=state17;
+    when state17=>
+        SCK<='0';
+        SS<='0';
+        MOSI<=datasection(0);
+        nextState<=state18;
+    when state18=>
+        SCK<='0';
+        SS<='1';
+        MOSI<='Z';
+        nextState<=state1;
+end case;
+
+end process States;
+
+ByteSelection: process(byteChoice)
+begin
+case byteChoice is
+   when 0 => dataSection<=x"76";
+   when 1 => dataSection<=x"76";
+   when 2 => dataSection<=x"76";
+   when 3 => dataSection<=x"76";
+   when 4 => dataSection<=x"76";
+   when 5 => dataSection <=x"0" & Data(15 downto 12);
+   when 6 => dataSection <=x"0" & Data(11 downto 8);
+   when 7 => dataSection <=x"0" & Data(7 downto 4);
+   when 8 => dataSection <=x"0" & Data(3 downto 0);
+   when others => dataSection <="11111111";
+end case;
+end process ByteSelection;
+
+
+end Behavioral;
+

SequenceController.vhd

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+----------------------------------------------------------------------------------
+--Code by: Zachary Rauen
+--Date: 10/6/14
+--Last Modified: 11/2/14
+--
+--Description: This is a sequence controller that uses three buttons as
+-- reset, reverse and a system enable. Using the clock this sytem will 
+-- generate an address for a ROM. However, this can be easily
+-- modified in order to create what is needed
+--
+--Version: 2.1
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity SequenceController is
+    Generic (NumOfSequences : integer := 8;
+             DesiredDisplaySpeed : integer := 100000;
+             InputClockSpeed : integer := 100000000);
+    Port ( ClockState : in std_logic;
+           Enabler : in std_logic;
+           Reset : in std_logic;
+           Reverse : in std_logic;
+           MemAddress : out integer := 0);
+end SequenceController;
+
+architecture Behavioral of SequenceController is
+
+signal clkMax : integer := InputClockSpeed/DesiredDisplaySpeed;
+signal clkCnt : integer := 0;
+signal displayCnt : integer := 0;
+signal StateEnable : std_logic;
+
+
+
+begin
+
+DisplaySpeed: process(ClockState)
+begin
+if rising_edge(ClockState) then
+    if Reset <= '0' then
+        if clkCnt = clkMax then
+            StateEnable <= '1';
+            clkCnt <= 0;
+        else
+            clkCnt<=clkCnt+1;
+            StateEnable <= '0';
+        end if;
+    else
+    clkCnt<=0;
+    end if;
+end if;
+
+end process DisplaySpeed;
+
+
+count: process(ClockState,StateEnable,Enabler,Reverse,Reset)
+begin
+        if Reset='1' then
+            displayCnt <= 0;
+        else
+        if Enabler = '1' then
+            if rising_edge(ClockState) AND StateEnable = '1' then
+                   if Reverse = '0' then
+                        if displayCnt = NumOfSequences then
+                            displayCnt <= 0;
+                        else
+                            displayCnt <= displayCnt + 1;
+                        end if;
+                    else 
+                        if displayCnt = 0 then
+                            displayCnt <= NumOfSequences;
+                        else
+                            displayCnt <= displayCnt - 1;
+                        end if;
+                    end if;
+            end if;
+        end if;
+    end if;
+MemAddress<=displayCnt;
+
+end process count;
+
+
+end Behavioral;