FPGA examples

This project is about FPGA hard blocks and board features. Examples ready to use and verified in hardware. The prefered HDL language is VHDL.

This project is mainly developed and mantained by the FPGA team of the Centre of Nano and Microelectronics CMNB of the National Institute of Industrial Technology INTI. Contributions are welcome.

Project Organization

Root directory:

• README.md: this file.
• LICENSE: of the project.
• CONTRIBUTING.md: How to Contribute to the project.
• CONTRIBUTORS.md: list of people who contributed to the project.
• shared/: Shared directory.
• fpga_lib/: git submodule fpga_lib.
  • Provides some portable HDL snippets.
• fpga_helpers/: git submodule fpga_helpers.
  • Provides Tcl scripts for synthesis and programming in a vendor independent way.
• examples/: contain a directory for each supported board by the project.
• Makefile: to automatize some tasks.
  • Run make submodule to init/update submodules.
  • Run make clean to delete all the files generated by the examples.
  • make contributors is used to generate CONTRIBUTORS.md.

example directory:

• README.md: list of available examples.
• Several vendor_board sub directories.

vendor_board directories:

• README.md: general information about features, Power Supply and Programming Options.
• Directories with examples for the given board.
• resources/: where to put how to obtain vendors files.
• Makefile: used to test prepare, synthesis and simulation, of all the examples of the board and to delete the generated files.

Examples directories:

• README.md: tutorial about how to run and reproduce the example.
• top.vhdl: top level.
• wrapper.vhdl [optional]: a wrapper for resources when complex, to have a cleanest top level.
• Makefile: to prepare vendors files (if needed), run synthesis and programming.
• options.tcl: used by Tcl script for synthesis and programming.
• Constraint file such as board.ext.
• testbench/ [optional]: only provided when useful (no trivial such as gpios) or posible (no license problems).
• NOTE: Makefile and options.tcl are used in conjunction with fpga_helpers/tcl, to have an unified, vendor independent way, of synthetize and programming the FPGA. You can take the HDL and constraints files and use them with your prefered vendor tool.

testbench directories:

• top_tb.vhdl: test or at least stimulus to see waveforms.
• Makefile: to run the test and see waveforms.
• files.ext: the files of the project.
• waves.ext: waveform to visualize.

License

FPGA Examples is licensed under the BSD 3-clause. See LICENSE for details.