Issues and References

FIR滤波器理论与实现代码（VHDL）

MATLAB 为定点滤波器生成 HDL 代码

Filter Design HDL Coder Documentatiom

FIR Filter (VHDL)

How to Implement FIR Filter in VHDL

https://www.jianshu.com/p/03cfc5d62794

How to read text file line by line in vhdl by clk?

File reading and writing in VHDL - Part 2

~~STIMULUS FILE READ IN TESTBENCH USING TEXTIO~~

http://www.ee.ic.ac.uk/pcheung/teaching/ee3_dsd/fir.pdf

https://www.allaboutcircuits.com/technical-articles/pipelined-direct-form-fir-versus-the-transposed-structure/

synthesis error

The problem is that, for synthesizing, Xilinx assumes every port is either of type std_logic or std_logic_vector (as it generates a new VHDL file that executed the synthesized model, including precise timing simulation). In order for it to work with a synthesizer, I should change the entity definition to std_logic_vector.

Why am I getting “Entity port d does not match with type unsigned of component portParsing…” when I try to simulate this VHDL?

• change data to std_logic_vector
• change coefficient to constant in type package

power too large issues

在constraint里写： create_clock -period （时钟周期，单位ns） [get_ports （端口名）] 然后再综合，可以约束时钟 例如：create_clock -period 20 [get_ports system_clk]

否则会默认用10GHz时钟，功耗非常大

这个是主时钟的语句，还有其他类型的时钟详见：https://blog.csdn.net/FPGADesigner/article/details/82871624?utm_medium=distribute.pc_relevant.none-task-blog-BlogCommendFromMachineLearnPai2-9&depth_1-utm_source=distribute.pc_relevant.none-task-blog-BlogCommendFromMachineLearnPai2-9

Show analog waveform in vivado