/
xtce_microcode.h
3723 lines (3669 loc) · 128 KB
/
xtce_microcode.h
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class Disassembler
{
public:
Disassembler() { reset(); }
void reset() { _byteCount = 0; }
String disassemble(Byte byte, bool firstByte)
{
String bytes;
if (firstByte) {
if (_byteCount != 0)
bytes = "!a";
_byteCount = 0;
}
_code[_byteCount] = byte;
++_byteCount;
_lastOffset = 0;
String instruction = disassembleInstruction();
if (_lastOffset >= _byteCount)
return bytes; // We don't have the complete instruction yet
_byteCount = 0;
for (int i = 0; i <= _lastOffset; ++i)
bytes += hex(_code[i], 2, false);
return bytes.alignLeft(12) + " " + instruction;
}
private:
String disassembleInstruction()
{
_wordSize = (opcode() & 1) != 0;
_doubleWord = false;
_offset = 1;
if ((opcode() & 0xc4) == 0)
return alu(op1()) + regMemPair();
if ((opcode() & 0xc6) == 4)
return alu(op1()) + accum() + ", " + imm();
if ((opcode() & 0xe7) == 6)
return "PUSH " + segreg(op1());
if ((opcode() & 0xe7) == 7)
return "POP " + segreg(op1());
if ((opcode() & 0xe7) == 0x26)
return segreg(op1() & 3) + ":";
if ((opcode() & 0xf8) == 0x40)
return "INC " + rwo();
if ((opcode() & 0xf8) == 0x48)
return "DEC " + rwo();
if ((opcode() & 0xf8) == 0x50)
return "PUSH " + rwo();
if ((opcode() & 0xf8) == 0x58)
return "POP " + rwo();
if ((opcode() & 0xfc) == 0x80)
return alu(reg()) + ea() + ", " +
(opcode() == 0x81 ? iw(true) : sb(true));
if ((opcode() & 0xfc) == 0x88)
return "MOV " + regMemPair();
if ((opcode() & 0xf8) == 0x90)
if (opcode() == 0x90)
return "NOP";
else
return "XCHG AX, " + rwo();
if ((opcode() & 0xf8) == 0xb0)
return "MOV " + rbo() + ", " + ib();
if ((opcode() & 0xf8) == 0xb8)
return "MOV " + rwo() + ", " + iw();
if ((opcode() & 0xfc) == 0xd0) {
static String shifts[8] = {
"ROL", "ROR", "RCL", "RCR", "SHL", "SHR", "SHL", "SAR"};
return shifts[reg()] + " " + ea() + ", " +
((op0() & 2) == 0 ? String("1") : byteRegs(1));
}
if ((opcode() & 0xf8) == 0xd8) {
_wordSize = false;
_doubleWord = true;
return String("ESC ") + op0() + ", " + reg() + ", " + ea();
}
if ((opcode() & 0xf6) == 0xe4)
return "IN " + accum() + ", " + port();
if ((opcode() & 0xf6) == 0xe6)
return "OUT " + port() + ", " + accum();
if ((opcode() & 0xe0) == 0x60) {
static String conds[16] = {
"O", "NO", "B", "AE", "E", "NE", "BE", "A",
"S", "NS", "P", "NP", "L", "GE", "LE", "G"};
return "J" + conds[opcode() & 0xf] + " " + cb();
}
switch (opcode()) {
case 0x27: return "DAA";
case 0x2f: return "DAS";
case 0x37: return "AAA";
case 0x3f: return "AAS";
case 0x84:
case 0x85: return "TEST " + regMemPair();
case 0x86:
case 0x87: return "XCHG " + regMemPair();
case 0x8c:
_wordSize = true;
return "MOV " + ea() + ", " + segreg(reg());
case 0x8d:
_doubleWord = true;
_wordSize = false;
return "LEA " + rw() + ", " + ea();
case 0x8e:
_wordSize = true;
return "MOV " + segreg(reg()) + ", " + ea();
case 0x8f: return "POP " + ea();
case 0x98: return "CBW";
case 0x99: return "CWD";
case 0x9a: return "CALL " + cp();
case 0x9b: return "WAIT";
case 0x9c: return "PUSHF";
case 0x9d: return "POPF";
case 0x9e: return "SAHF";
case 0x9f: return "LAHF";
case 0xa0:
case 0xa1: return "MOV " + accum() + ", " + size() + "[" + iw() + "]";
case 0xa2:
case 0xa3: return "MOV " + size() + "[" + iw() + "], " + accum();
case 0xa4:
case 0xa5: return "MOVS" + size();
case 0xa6:
case 0xa7: return "CMPS" + size();
case 0xa8:
case 0xa9: return "TEST " + accum() + ", " + imm();
case 0xaa:
case 0xab: return "STOS" + size();
case 0xac:
case 0xad: return "LODS" + size();
case 0xae:
case 0xaf: return "SCAS" + size();
case 0xc0:
case 0xc2: return "RET " + iw();
case 0xc1:
case 0xc3: return "RET";
case 0xc4: _doubleWord = true; return "LES " + rw() + ", " + ea();
case 0xc5:
_doubleWord = true;
_wordSize = false;
return "LDS " + rw() + ", " + ea();
case 0xc6:
case 0xc7: return "MOV " + ea() + ", " + imm(true);
case 0xc8:
case 0xca: return "RETF " + iw();
case 0xc9:
case 0xcb: return "RETF";
case 0xcc: return "INT 3";
case 0xcd: return "INT " + ib();
case 0xce: return "INTO";
case 0xcf: return "IRET";
case 0xd4: return "AAM " + ib();
case 0xd5: return "AAD " + ib();
case 0xd6: return "SALC";
case 0xd7: return "XLATB";
case 0xe0: return "LOOPNE " + cb();
case 0xe1: return "LOOPE " + cb();
case 0xe2: return "LOOP " + cb();
case 0xe3: return "JCXZ " + cb();
case 0xe8: return "CALL " + cw();
case 0xe9: return "JMP " + cw();
case 0xea: return "JMP " + cp();
case 0xeb: return "JMP " + cb();
case 0xf0:
case 0xf1: return "LOCK";
case 0xf2: return "REPNE ";
case 0xf3: return "REP ";
case 0xf4: return "HLT";
case 0xf5: return "CMC";
case 0xf6:
case 0xf7:
switch (reg()) {
case 0:
case 1: return "TEST " + ea() + ", " + imm(true);
case 2: return "NOT " + ea();
case 3: return "NEG " + ea();
case 4: return "MUL " + ea();
case 5: return "IMUL " + ea();
case 6: return "DIV " + ea();
case 7: return "IDIV " + ea();
}
case 0xf8: return "CLC";
case 0xf9: return "STC";
case 0xfa: return "CLI";
case 0xfb: return "STI";
case 0xfc: return "CLD";
case 0xfd: return "STD";
case 0xfe:
case 0xff:
switch (reg()) {
case 0: return "INC " + ea();
case 1: return "DEC " + ea();
case 2: return "CALL " + ea();
case 3: _doubleWord = true; return "CALL " + ea();
case 4: return "JMP " + ea();
case 5: _doubleWord = true; return "JMP " + ea();
case 6: return "PUSH " + ea();
case 7: return "??? " + ea();
}
}
return "!b";
}
UInt8 getByte(int offset)
{
_lastOffset = max(_lastOffset, offset);
return _code[offset];
}
UInt16 getWord(int offset)
{
return getByte(offset) | (getByte(offset + 1) << 8);
}
String regMemPair()
{
if ((op0() & 2) == 0)
return ea() + ", " + r();
return r() + ", " + ea();
}
String r() { return !_wordSize ? rb() : rw(); }
String rb() { return byteRegs(reg()); }
String rw() { return wordRegs(reg()); }
String rbo() { return byteRegs(op0()); }
String rwo() { return wordRegs(op0()); }
String byteRegs(int r)
{
static String b[8] = {"AL", "CL", "DL", "BL", "AH", "CH", "DH", "BH"};
return b[r];
}
String wordRegs(int r)
{
static String w[8] = {"AX", "CX", "DX", "BX", "SP", "BP", "SI", "DI"};
return w[r];
}
String ea()
{
String s;
switch (mod()) {
case 0: s = disp(); break;
case 1: s = disp() + sb(); _offset = 3; break;
case 2: s = disp() + "+" + iw(); _offset = 4; break;
case 3: return !_wordSize ? byteRegs(rm()) : wordRegs(rm());
}
return size() + "[" + s + "]";
}
String size()
{
if (!_doubleWord)
return (!_wordSize ? "B" : "W");
else
return (!_wordSize ? "" : "D");
}
String disp()
{
static String d[8] = {
"BX+SI", "BX+DI", "BP+SI", "BP+DI", "SI", "DI", "BP", "BX"};
if (mod() == 0 && rm() == 6) {
String s = iw();
_offset = 4;
return s;
}
return d[rm()];
}
String alu(int op)
{
static String o[8] = {
"ADD ", "OR ", "ADC ", "SBB ", "AND ", "SUB ", "XOR ", "CMP "};
return o[op];
}
Byte opcode() { return getByte(0); }
int op0() { return opcode() & 7; }
int op1() { return (opcode() >> 3) & 7; }
Byte modRM() { _offset = 2; return getByte(1); }
int mod() { return modRM() >> 6; }
int reg() { return (modRM() >> 3) & 7; }
int rm() { return modRM() & 7; }
String imm(bool m = false) { return !_wordSize ? ib(m) : iw(m); }
String iw(bool m = false)
{
if (m)
ea();
return hex(getWord(_offset), 4, false);
}
String ib(bool m = false)
{
if (m)
ea();
return hex(getByte(_offset), 2, false);
}
String sb(bool m = false)
{
if (m)
ea();
UInt8 byte = getByte(_offset);
if ((byte & 0x80) == 0)
return "+" + hex(byte, 2, false);
return "-" + hex(-byte, 2, false);
}
String accum() { return !_wordSize ? "AL" : "AX"; }
String segreg(int r)
{
static String sr[8] = {"ES", "CS", "SS", "DS", "??", "??", "??", "??"};
return sr[r];
}
String cb()
{
return "IP" + sb();
//hex(_address + static_cast<SInt8>(getByte(_offset)), 4, false);
}
String cw()
{
return "IP+" + iw();
//return hex(_address + getWord(_offset), 4, false);
}
String cp()
{
return hex(getWord(_offset + 2), 4, false) + ":" +
hex(getWord(_offset), 4, false);
}
String port() { return ((op1() & 1) == 0 ? ib() : wordRegs(2)); }
UInt16 _ip;
UInt8 _code[6];
int _byteCount;
bool _wordSize;
bool _doubleWord;
int _offset;
int _lastOffset;
};
class SnifferDecoder
{
public:
void reset()
{
_cpu_rqgt0 = false; // Used by 8087 for bus mastering, NYI
_cpu_ready = true; // Used for DMA and wait states
_cpu_test = false; // Used by 8087 for synchronization, NYI
_cpu_lock = false;
_bus_dma = 0; // NYI
_dmas = 0;
_bus_irq = 0xfc; // NYI
_int = false;
_bus_iochrdy = true; // Used for wait states, NYI
_bus_aen = false; // Used for DMA
_bus_tc = false; // Used for DMA, NYI
_cga = 0;
_t = 0;
_tNext = 0;
_d = -1;
_queueLength = 0;
_lastS = 0;
_cpu_s = 7;
_cpu_qs = 0;
_cpu_next_qs = 0;
_disassembler.reset();
}
String getLine()
{
static const char qsc[] = ".IES";
static const char sc[] = "ARWHCrwp";
static const char dmasc[] = " h:H";
String line;
if (_cpuDataFloating)
line = String(hex(_cpu_ad >> 8, 3, false)) + "??";
else
line = String(hex(_cpu_ad, 5, false));
line += " " +
codePoint(qsc[_cpu_qs]) + codePoint(sc[_cpu_s]) +
(_cpu_rqgt0 ? "G" : ".") + (_cpu_ready ? "." : "z") +
(_cpu_test ? "T" : ".") + (_cpu_lock ? "L" : ".") +
" " + hex(_bus_address, 5, false) + " ";
if (_isaDataFloating)
line += "??";
else
line += hex(_bus_data, 2, false);
line += " " + hex(_bus_dma, 2, false) + codePoint(dmasc[_dmas]) +
" " + hex(_bus_irq, 2, false) + (_int ? "I" : " ") + " " +
hex(_bus_pit, 1, false) + hex(_cga, 1, false) + " " + (_bus_ior ? "R" : ".") +
(_bus_iow ? "W" : ".") + (_bus_memr ? "r" : ".") +
(_bus_memw ? "w" : ".") + (_bus_iochrdy ? "." : "z") +
(_bus_aen ? "D" : ".") +
(_bus_tc ? "T" : ".");
line += " ";
if (_cpu_s != 7 && _cpu_s != 3)
switch (_tNext) {
case 0:
case 4:
// T1 state occurs after transition out of passive
_tNext = 1;
break;
case 1:
_tNext = 2;
break;
case 2:
_tNext = 3;
break;
case 3:
_tNext = 5;
break;
}
else
switch (_t) {
case 4:
_d = -1;
case 0:
_tNext = 0;
break;
case 1:
case 2:
_tNext = 6;
break;
case 3:
case 5:
_d = -1;
_tNext = 4;
break;
}
switch (_t) {
case 0: line += " "; break;
case 1: line += "T1"; break;
case 2: line += "T2"; break;
case 3: line += "T3"; break;
case 4: line += "T4"; break;
case 5: line += "Tw"; break;
default: line += "!c"; _tNext = 0; break;
}
line += " ";
if (_bus_aen)
switch (_d) {
// This is a bit of a hack since we don't have access
// to the right lines to determine the DMA state
// properly. This probably breaks for memory-to-memory
// copies.
case -1: _d = 0; break;
case 0: _d = 1; break;
case 1: _d = 2; break;
case 2: _d = 3; break;
case 3:
case 5:
if ((_bus_iow && _bus_memr) || (_bus_ior && _bus_memw))
_d = 4;
else
_d = 5;
break;
case 4:
_d = -1;
}
switch (_d) {
case -1: line += " "; break;
case 0: line += "S0"; break;
case 1: line += "S1"; break;
case 2: line += "S2"; break;
case 3: line += "S3"; break;
case 4: line += "S4"; break;
case 5: line += "SW"; break;
default: line += "!d"; _t = 0; break;
}
line += " ";
String instruction;
if (_cpu_qs != 0) {
if (_cpu_qs == 2)
_queueLength = 0;
else {
Byte b = _queue[0];
for (int i = 0; i < 3; ++i)
_queue[i] = _queue[i + 1];
--_queueLength;
if (_queueLength < 0) {
line += "!g";
_queueLength = 0;
}
instruction = _disassembler.disassemble(b, _cpu_qs == 1);
}
}
if (_tNext == 4 || _d == 4) {
if (_tNext == 4 && _d == 4)
line += "!e";
String seg;
switch (_cpu_ad & 0x30000) {
case 0x00000: seg = "ES "; break;
case 0x10000: seg = "SS "; break;
case 0x20000: seg = "CS "; break;
case 0x30000: seg = "DS "; break;
}
String type = "-";
if (_lastS == 0)
line += hex(_bus_data, 2, false) + " <-i ";
else {
if (_lastS == 4) {
type = "f";
seg = " ";
}
if (_d == 4) {
type = "d";
seg = " ";
}
line += hex(_bus_data, 2, false) + " ";
if (_bus_ior || _bus_memr)
line += "<-" + type + " ";
else
line += type + "-> ";
if (_bus_memr || _bus_memw)
line += "[" + seg + hex(_bus_address, 5, false) + "]";
else
line += "port[" + hex(_bus_address, 4, false) + "]";
if (_lastS == 4 && _d != 4) {
if (_queueLength >= 4)
line += "!f";
else {
_queue[_queueLength] = _bus_data;
++_queueLength;
}
}
}
line += " ";
}
else
line += " ";
if (_cpu_qs != 0)
line += codePoint(qsc[_cpu_qs]);
else
line += " ";
line += " " + instruction;
_lastS = _cpu_s;
_t = _tNext;
if (_t == 4 || _d == 4) {
_bus_ior = false;
_bus_iow = false;
_bus_memr = false;
_bus_memw = false;
}
// 8086 Family Users Manual page 4-37 clock cycle 12: "remember
// the queue status lines indicate queue activity that has occurred in
// the previous clock cycle".
_cpu_qs = _cpu_next_qs;
_cpu_next_qs = 0;
return line;
}
void queueOperation(int qs) { _cpu_next_qs = qs; }
void setStatus(int s) { _cpu_s = s; }
void setStatusHigh(int segment)
{
_cpu_ad &= 0xcffff;
switch (segment) {
case 0: // ES
break;
case 2: // SS
_cpu_ad |= 0x10000;
break;
case 3: // DS
_cpu_ad |= 0x30000;
break;
default: // CS or none
_cpu_ad |= 0x20000;
break;
}
setBusFloating();
}
void setInterruptFlag(bool intf)
{
_cpu_ad = (_cpu_ad & 0xbffff) | (intf ? 0x40000 : 0);
}
void setBusOperation(int s)
{
switch (s) {
case 1: _bus_ior = true; break;
case 2: _bus_iow = true; break;
case 4:
case 5: _bus_memr = true; break;
case 6: _bus_memw = true; break;
}
}
void setData(Byte data)
{
_cpu_ad = (_cpu_ad & 0xfff00) | data;
_bus_data = data;
_cpuDataFloating = false;
_isaDataFloating = false;
}
void setAddress(UInt32 address)
{
_cpu_ad = address;
_bus_address = address;
_cpuDataFloating = false;
}
void setBusFloating()
{
_cpuDataFloating = true;
_isaDataFloating = true;
}
void setPITBits(int bits) { _bus_pit = bits; }
void setAEN(bool aen) { _bus_aen = aen; }
void setDMA(UInt8 dma) { _bus_dma = dma; }
void setReady(bool ready) { _cpu_ready = ready; }
void setLock(bool lock) { _cpu_lock = lock; }
void setDMAS(UInt8 dmas) { _dmas = dmas; }
void setIRQs(UInt8 irq) { _bus_irq = irq; }
void setINT(bool intrq) { _int = intrq; }
void setCGA(UInt8 cga) { _cga = cga; }
private:
Disassembler _disassembler;
// Internal variables that we use to keep track of what's going on in order
// to be able to print useful logs.
int _t; // 0 = Tidle, 1 = T1, 2 = T2, 3 = T3, 4 = T4, 5 = Tw
int _tNext;
int _d; // -1 = SI, 0 = S0, 1 = S1, 2 = S2, 3 = S3, 4 = S4, 5 = SW
Byte _queue[4];
int _queueLength;
int _lastS;
// These represent the CPU and ISA bus pins used to create the sniffer
// logs.
UInt32 _cpu_ad;
// A19/S6 O ADDRESS/STATUS: During T1, these are the four most significant address lines for memory operations. During I/O operations, these lines are LOW. During memory and I/O operations, status information is available on these lines during T2, T3, Tw, and T4. S6 is always low.
// A18/S5 O The status of the interrupt enable flag bit (S5) is updated at the beginning of each clock cycle.
// A17/S4 O S4*2+S3 0 = Alternate Data, 1 = Stack, 2 = Code or None, 3 = Data
// A16/S3 O
// A15..A8 O ADDRESS BUS: These lines provide address bits 8 through 15 for the entire bus cycle (T1±T4). These lines do not have to be latched by ALE to remain valid. A15±A8 are active HIGH and float to 3-state OFF during interrupt acknowledge and local bus ``hold acknowledge''.
// AD7..AD0 IO ADDRESS DATA BUS: These lines constitute the time multiplexed memory/IO address (T1) and data (T2, T3, Tw, T4) bus. These lines are active HIGH and float to 3-state OFF during interrupt acknowledge and local bus ``hold acknowledge''.
UInt8 _cpu_qs;
UInt8 _cpu_next_qs;
// QS0 O QUEUE STATUS: provide status to allow external tracking of the internal 8088 instruction queue. The queue status is valid during the CLK cycle after which the queue operation is performed.
// QS1 0 = No operation, 1 = First Byte of Opcode from Queue, 2 = Empty the Queue, 3 = Subsequent Byte from Queue
UInt8 _cpu_s;
// -S0 O STATUS: is active during clock high of T4, T1, and T2, and is returned to the passive state (1,1,1) during T3 or during Tw when READY is HIGH. This status is used by the 8288 bus controller to generate all memory and I/O access control signals. Any change by S2, S1, or S0 during T4 is used to indicate the beginning of a bus cycle, and the return to the passive state in T3 and Tw is used to indicate the end of a bus cycle. These signals float to 3-state OFF during ``hold acknowledge''. During the first clock cycle after RESET becomes active, these signals are active HIGH. After this first clock, they float to 3-state OFF.
// -S1 0 = Interrupt Acknowledge, 1 = Read I/O Port, 2 = Write I/O Port, 3 = Halt, 4 = Code Access, 5 = Read Memory, 6 = Write Memory, 7 = Passive
// -S2
bool _cpu_rqgt0; // -RQ/-GT0 !87 IO REQUEST/GRANT: pins are used by other local bus masters to force the processor to release the local bus at the end of the processor's current bus cycle. Each pin is bidirectional with RQ/GT0 having higher priority than RQ/GT1. RQ/GT has an internal pull-up resistor, so may be left unconnected.
bool _cpu_ready; // READY I READY: is the acknowledgement from the addressed memory or I/O device that it will complete the data transfer. The RDY signal from memory or I/O is synchronized by the 8284 clock generator to form READY. This signal is active HIGH. The 8088 READY input is not synchronized. Correct operation is not guaranteed if the set up and hold times are not met.
bool _cpu_test; // -TEST I TEST: input is examined by the ``wait for test'' instruction. If the TEST input is LOW, execution continues, otherwise the processor waits in an ``idle'' state. This input is synchronized internally during each clock cycle on the leading edge of CLK.
bool _cpu_lock; // -LOCK !87 O LOCK: indicates that other system bus masters are not to gain control of the system bus while LOCK is active (LOW). The LOCK signal is activated by the ``LOCK'' prefix instruction and remains active until the completion of the next instruction. This signal is active LOW, and floats to 3-state off in ``hold acknowledge''.
UInt32 _bus_address;
// +A19..+A0 O Address bits: These lines are used to address memory and I/O devices within the system. These lines are generated by either the processor or DMA controller.
UInt8 _bus_data;
// +D7..+D0 IO Data bits: These lines provide data bus bits 0 to 7 for the processor, memory, and I/O devices.
UInt8 _bus_dma;
// +DRQ0 JP6/1 == U28.19 == U73.9
// +DRQ1..+DRQ3 I DMA Request: These lines are asynchronous channel requests used by peripheral devices to gain DMA service. They are prioritized with DRQ3 being the lowest and DRQl being the highest. A request is generated by bringing a DRQ line to an active level (high). A DRQ line must be held high until the corresponding DACK line goes active.
// -DACK0..-DACK3 O -DMA Acknowledge: These lines are used to acknowledge DMA requests (DRQ1-DRQ3) and to refresh system dynamic memory (DACK0). They are active low.
UInt8 _dmas; // JP9/4 HRQ DMA (bit 0), JP4/1 HOLDA (bit 1)
UInt8 _bus_irq;
// +IRQ0..+IRQ7 I Interrupt Request lines: These lines are used to signal the processor that an I/O device requires attention. An Interrupt Request is generated by raising an IRQ line (low to high) and holding it high until it is acknowledged by the processor (interrupt service routine).
bool _int; // JP9/1 INT
UInt8 _cga; // JP7/2 CGA HCLK (bit 0), JP7/1 CGA LCLK (bit 1)
UInt8 _bus_pit; // clock, gate, output
bool _bus_ior; // -IOR O -I/O Read Command: This command line instructs an I/O device to drive its data onto the data bus. It may be driven by the processor or the DMA controller. This signal is active low.
bool _bus_iow; // -IOW O -I/O Write Command: This command line instructs an I/O device to read the data on the data bus. It may be driven by the processor or the DMA controller. This signal is active low.
bool _bus_memr; // -MEMR O Memory Read Command: This command line instructs the memory to drive its data onto the data bus. It may be driven by the processor or the DMA controller. This signal is active low.
bool _bus_memw; // -MEMW O Memory Write Command: This command line instructs the memory to store the data present on the data bus. It may be driven by the processor or the DMA controller. This signal is active low.
bool _bus_iochrdy; // +I/O CH RDY I I/O Channel Ready: This line, normally high (ready), is pulled low (not ready) by a memory or I/O device to lengthen I/O or memory cycles. It allows slower devices to attach to the I/O channel with a minimum of difficulty. Any slow device using this line should drive it low immediately upon detecting a valid address and a read or write command. This line should never be held low longer than 10 clock cycles. Machine cycles (I/O or memory) are extended by an integral number of CLK cycles (210 ns).
bool _bus_aen; // +AEN O Address Enable: This line is used to de-gate the processor and other devices from the I/O channel to allow DMA transfers to take place. When this line is active (high), the DMA controller has control of the address bus, data bus, read command lines (memory and I/O), and the write command lines (memory and I/O).
bool _bus_tc; // +T/C O Terminal Count: This line provides a pulse when the terminal count for any DMA channel is reached. This signal is active high.
bool _cpuDataFloating;
bool _isaDataFloating;
};
class PITEmulator
{
public:
void reset()
{
for (int i = 0; i < 3; ++i)
_counters[i].reset();
}
void stubInit()
{
for (int i = 0; i < 3; ++i)
_counters[i].stubInit();
}
void write(int address, Byte data)
{
if (address == 3) {
int counter = data >> 6;
if (counter == 3)
return;
_counters[counter].control(data & 0x3f);
}
else
_counters[address].write(data);
}
Byte read(int address)
{
if (address == 3)
return 0xff;
return _counters[address].read();
}
void wait()
{
for (int i = 0; i < 3; ++i)
_counters[i].wait();
}
void setGate(int counter, bool gate)
{
_counters[counter].setGate(gate);
}
bool getOutput(int counter) { return _counters[counter]._output; }
//int getMode(int counter) { return _counters[counter]._control; }
private:
enum State
{
stateWaitingForCount,
stateCounting,
stateWaitingForGate,
stateGateRose,
stateLoadDelay,
statePulsing
};
struct Counter
{
void reset()
{
_value = 0;
_count = 0;
_firstByte = true;
_latched = false;
_output = true;
_control = 0x30;
_state = stateWaitingForCount;
}
void stubInit()
{
_value = 0xffff;
_count = 0xffff;
_firstByte = true;
_latched = false;
_output = true;
_control = 0x34;
_state = stateCounting;
_gate = true;
}
void write(Byte data)
{
_writeByte = data;
_haveWriteByte = true;
}
Byte read()
{
if (!_latched) {
// TODO: corrupt countdown in a deterministic but
// non-trivial way.
_latch = _count;
}
switch (_control & 0x30) {
case 0x10:
_latched = false;
return _latch & 0xff;
case 0x20:
_latched = false;
return _latch >> 8;
case 0x30:
if (_firstByte) {
_firstByte = false;
return _latch & 0xff;
}
_firstByte = true;
_latched = false;
return _latch >> 8;
}
// This should never happen.
return 0;
}
void wait()
{
switch (_control & 0x0e) {
case 0x00: // Interrupt on Terminal Count
if (_state == stateLoadDelay) {
_state = stateCounting;
_value = _count;
break;
}
if (_gate && _state == stateCounting) {
countDown();
if (_value == 0)
_output = true;
}
break;
case 0x02: // Programmable One-Shot
if (_state == stateLoadDelay) {
_state = stateWaitingForGate;
break;
}
if (_state == stateGateRose) {
_output = false;
_value = _count;
_state = stateCounting;
}
countDown();
if (_value == 0) {
_output = true;
_state = stateWaitingForGate;
}
break;
case 0x04:
case 0x0c: // Rate Generator
if (_state == stateLoadDelay) {
_state = stateCounting;
_value = _count;
break;
}
if (_gate && _state == stateCounting) {
countDown();
if (_value == 1)
_output = false;
if (_value == 0) {
_output = true;
_value = _count;
}
}
break;
case 0x06:
case 0x0e: // Square Wave Rate Generator
if (_state == stateLoadDelay) {
_state = stateCounting;
_value = _count;
break;
}
if (_gate && _state == stateCounting) {
if ((_value & 1) != 0) {
if (!_output) {
countDown();
countDown();
}
}
else
countDown();
countDown();
if (_value == 0) {
_output = !_output;
_value = _count;
}
}
break;
case 0x08: // Software Triggered Strobe
if (_state == stateLoadDelay) {
_state = stateCounting;
_value = _count;
break;
}
if (_state == statePulsing) {
_output = true;
_state = stateWaitingForCount;
}
if (_gate && _state == stateCounting) {
countDown();
if (_value == 0) {
_output = false;
_state = statePulsing;
}
}
break;
case 0x0a: // Hardware Triggered Strobe
if (_state == stateLoadDelay) {
_state = stateWaitingForGate;
break;
}
if (_state == statePulsing) {
_output = true;
_state = stateWaitingForCount;
}
if (_state == stateGateRose) {
_output = false;
_value = _count;
_state = stateCounting;
}
if (_state == stateCounting) {
countDown();
if (_value == 1)
_output = false;
if (_value == 0) {
_output = true;
_state = stateWaitingForGate;
}
}
break;
}
if (_haveWriteByte) {
_haveWriteByte = false;
switch (_control & 0x30) {
case 0x10:
load(_writeByte);
break;
case 0x20:
load(_writeByte << 8);
break;
case 0x30:
if (_firstByte) {
_lowByte = _writeByte;
_firstByte = false;
}
else {
load((_writeByte << 8) + _lowByte);
_firstByte = true;
}
break;
}
}
}
void countDown()
{
if ((_control & 1) == 0) {
--_value;
return;
}
if ((_value & 0xf) != 0) {
--_value;
return;
}
if ((_value & 0xf0) != 0) {
_value -= (0x10 - 9);
return;
}
if ((_value & 0xf00) != 0) {
_value -= (0x100 - 0x99);
return;
}
_value -= (0x1000 - 0x999);
}
void load(Word count)
{
_count = count;
switch (_control & 0x0e) {
case 0x00: // Interrupt on Terminal Count
if (_state == stateWaitingForCount)
_state = stateLoadDelay;
_output = false;
break;
case 0x02: // Programmable One-Shot
if (_state != stateCounting)
_state = stateLoadDelay;
break;
case 0x04:
case 0x0c: // Rate Generator
if (_state == stateWaitingForCount)
_state = stateLoadDelay;
break;
case 0x06:
case 0x0e: // Square Wave Rate Generator
if (_state == stateWaitingForCount)
_state = stateLoadDelay;
break;
case 0x08: // Software Triggered Strobe
if (_state == stateWaitingForCount)
_state = stateLoadDelay;
break;
case 0x0a: // Hardware Triggered Strobe
if (_state != stateCounting)
_state = stateLoadDelay;
break;
}
}
void control(Byte control)
{
int command = control & 0x30;
if (command == 0) {
_latch = _value;
_latched = true;
return;
}
_control = control;
_firstByte = true;
_latched = false;
_state = stateWaitingForCount;
switch (_control & 0x0e) {
case 0x00: // Interrupt on Terminal Count
_output = false;
break;
case 0x02: // Programmable One-Shot
_output = true;
break;
case 0x04:
case 0x0c: // Rate Generator
_output = true;
break;
case 0x06:
case 0x0e: // Square Wave Rate Generator
_output = true;
break;
case 0x08: // Software Triggered Strobe
_output = true;
break;
case 0x0a: // Hardware Triggered Strobe
_output = true;
break;
}
}
void setGate(bool gate)
{
if (_gate == gate)
return;
switch (_control & 0x0e) {
case 0x00: // Interrupt on Terminal Count
break;
case 0x02: // Programmable One-Shot
if (gate)
_state = stateGateRose;
break;
case 0x04:
case 0x0c: // Rate Generator
if (!gate)
_output = true;
else
_value = _count;
break;