fix riscv build: add enable_pmp to Platform and properly eval privile…

…ge in Isa_model conversions
rems-project · Jun 28, 2019 · a72c696 · a72c696
1 parent fe4f286
commit a72c696
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Showing 2 changed files with 3 additions and 1 deletion.
diff --git a/src_top/isa_model.ml b/src_top/isa_model.ml
@@ -287,7 +287,7 @@ module Make (ISADefs: ISADefs) (TransSail: Trans.TransSail) : S = struct
       if rv.rv_start <> 0 || rv.rv_dir <> D_decreasing then failwith "invalid vector interp2__regval_to_interp" else
         match List.length (rv.rv_bits) with
         | 1 -> V_bool (bool_from_bitl (List.hd rv.rv_bits))
-        | 2 -> Riscv_toFromInterp2.privilegeToInterpValue (Riscv.privLevel_of_bits (Lem.wordFromBitlist (List.map bool_from_bitl rv.rv_bits)))
+        | 2 -> Riscv_toFromInterp2.privilegeToInterpValue (InstructionSemantics.continue_to_sail2_done "privilege" (Riscv.privLevel_of_bits (Lem.wordFromBitlist (List.map bool_from_bitl rv.rv_bits))))
         | 64 -> V_vector (List.map (fun b -> bool_from_bitl b |> interp2__bool_to_bit) rv.rv_bits)
         | 65 -> V_record (StringMap.add "Medeleg_chunk_0" (V_vector (List.map (fun b -> bool_from_bitl b |> interp2__bool_to_bit) (Util.drop 1 rv.rv_bits))) StringMap.empty)
         | 66 -> V_record (StringMap.add "Sedeleg_chunk_0" (V_vector (List.map (fun b -> bool_from_bitl b |> interp2__bool_to_bit) (Util.drop 2 rv.rv_bits))) StringMap.empty)

diff --git a/src_top/platform.ml b/src_top/platform.ml
@@ -59,3 +59,5 @@ let mtval_has_illegal_inst_bits () = false
 let enable_writable_misa () = true
 
 let enable_rvc () = true
+
+let enable_pmp () = false