Update IPL and Secure Monitor Rev1.0.19 rev2

 [IPL]
 - Add processing of Suspend To RAM for E3.
 - Update DDR setting for E3(rev0.06).
 - Update E3 Ver1.0 QoS setting rev.0.02.
 - Update M3N Ver.1.0 QoS setting rev.0.06.
 - Fix the LSI_CUT judgement of PFC setting.
 - Change definition of end address of system ram for BL2.

 [Secure Monitor]
 - Fix the primary CPU decision function that runs at startup.
 - Change the SelfRefresh sequence of Suspend To RAM.
 - Add the DVFS SCL setting of E3.

bl2/bl2.ld.S

@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.
- * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -17,7 +17,7 @@ ENTRY(bl2_entrypoint)
 
 MEMORY {
 #if PLAT_rcar
-    RAM (rwx): ORIGIN = BL2_BASE, LENGTH = DEVICE_RCAR_BASE2 - BL2_BASE
+    RAM (rwx): ORIGIN = BL2_BASE, LENGTH = RCAR_SYSRAM_LIMIT - BL2_BASE
 #else
     RAM (rwx): ORIGIN = BL2_BASE, LENGTH = BL2_LIMIT - BL2_BASE
 #endif

plat/renesas/rcar/aarch64/rcar_helpers.S

@@ -215,75 +215,11 @@ rep_exec_end:
 	ret
 endfunc plat_report_exception
 
-	/*
-	 *	Starting CPU is ...
-	 *		MD7=1 and MD6=1 of MODEMR	: CortexR7
-	 *		MD7=1 and MD6=0 of MODEMR	: Reserved
-	 *		MD7=0 and MD6=1 of MODEMR	: CortexA53
-	 *		MD7=0 and MD6=0 of MODEMR	: CortexA57
-	 *
-	 *	Information of MPIDR_EL1
-	 *		affinity level 1(bit15-8) = 1	: CortexA53
-	 *		affinity level 1(bit15-8) = 0	: CortexA57
-	 *
-	 */
 
 func platform_is_primary_cpu
-	/*
-	 * Get MD6 and MD7 of MODEMR, then move MD6 to bit0 and move MD7 to bit1 of x1
-	 */
-	ldr	x1, =RCAR_MODEMR		/* x1 <- address of MODEMR register	*/
-	ldr	w2, [x1]			/* Get the data of MODEMR -> x2		*/
-	mov	x1, #0x00c0			/* move MD6(0x0040) and MD7(0x0080)	*/
-	and	x1, x2, x1			/* Get MD6 and MD7 information -> x1	*/
-	lsr	x1, x1, #6			/* MD6->bit0, MD7->bit1			*/
-	/*
-	 * Get data of affinity level 1 of MPIDR_EL1, then move data to bit7-0 of x2
-	 */
-	mov	x2, #MPIDR_CLUSTER_MASK		/* MPIDR_CLUSTER_MASK=0xFF00 -> x2	*/
-	and	x2, x0, x2			/* Get the affinity level 1 -> x2	*/
-	lsr	x2, x2, #MPIDR_AFFINITY_BITS	/* affinity level 1 -> bit7-0 of x2	*/
-	/*
-	 * Check the starting CPU by MD7
-	 */
-	mov	x3, #0x0002			/* for test the MD7			*/
-	and	x3, x1, x3			/* MD7 information -> x3(0 or not)	*/
-	cbnz	x3, primary_check		/* Starting CPU is CortexR7		*/
-	/*
-	 * CA53 check
-	 */
-	mov	x3, #0x0003			/* MD6 and MD7				*/
-	and	x3, x1, x3
-	cmp	x3, #0x0001			/* If starting CPU is CortexA53		*/
-	bne	checkCA57			/*  is not then branch to check CA57	*/
-
-	ldr	x1, =RCAR_PRR
-	ldr	w1, [x1]			/* Read PRR */
-	ubfx	x1, x1, #31, #1			/* Mask PRR.bit31 */
-	cbnz	x1, primary_check		/* If bit31 is 0b1, Cortex-A57 cluster none. */
-
-	cmp	x2, #0x0001			/* If affinity level 1 is CortexA53	*/
-	beq	primary_check			/*  CPU is CortexA53			*/
-	b	platform_is_secondary		/* It is secondary			*/
-	/*
-	 * CA57 check
-	 */
-checkCA57:
-	cmp	x3, #0x0000			/* If starting CPU is CortexA57		*/
-	bne	platform_is_secondary
-	cmp	x2, #0x0000			/* If affinity level 1 is CortexA57	*/
-	beq	primary_check			/*  CPU is CortexA57			*/
-	/*
-	 * This CPU is secondary
-	 */
-platform_is_secondary:
-	mov	x0, #0				/* This cpu is secondary		*/
-	b	primary_check_exit		/* return				*/
-primary_check:
 	and	x0, x0, # MPIDR_CPU_MASK	/* Get the bit7-0 of MPIDR_EL1 -> x0	*/
 	cmp	x0, #RCAR_PRIMARY_CPU		/* x0 = 0 (primary CPU)?		*/
 	cset	x0, eq				/* If x0 is 0 carry bit set		*/
-primary_check_exit:
 	ret
 endfunc platform_is_primary_cpu
 

plat/renesas/rcar/bl2_cpg_init.c

@@ -42,8 +42,15 @@ static void bl2_secure_cpg_init(void)
 	cpg_write(SCMSTPCR0,	0xFFFFFFFFU);
 	/* Secure Module Stop Control Register 1 */
 	cpg_write(SCMSTPCR1,	0xFFFFFFFFU);
+
+#if (RCAR_LSI == RCAR_E3)
+	/* Secure Module Stop Control Register 2 */
+	cpg_write(SCMSTPCR2,	0xEFFFFFFFU);
+#else /* RCAR_LSI == RCAR_E3 */
 	/* Secure Module Stop Control Register 2 */
 	cpg_write(SCMSTPCR2,	0xEBFFFFFFU);
+#endif /* RCAR_LSI == RCAR_E3 */
+
 	/* Secure Module Stop Control Register 3 */
 	cpg_write(SCMSTPCR3,	0xFFFFFFFFU);
 	/* Secure Module Stop Control Register 4 */
@@ -66,8 +73,15 @@ static void bl2_secure_cpg_init(void)
 	cpg_write(SCSRSTECR0,	0x00000000U);
 	/* Secure Software Reset Access Enable Control Register 1 */
 	cpg_write(SCSRSTECR1,	0x00000000U);
+
+#if (RCAR_LSI == RCAR_E3)
+	/* Secure Software Reset Access Enable Control Register 2 */
+	cpg_write(SCSRSTECR2,	0x10000000U);
+#else /* RCAR_LSI == RCAR_E3 */
 	/* Secure Software Reset Access Enable Control Register 2 */
 	cpg_write(SCSRSTECR2,	0x14000000U);
+#endif /* RCAR_LSI == RCAR_E3 */
+
 	/* Secure Software Reset Access Enable Control Register 3 */
 	cpg_write(SCSRSTECR3,	0x00000000U);
 	/* Secure Software Reset Access Enable Control Register 4 */
@@ -298,7 +312,7 @@ static void bl2_realtime_cpg_init_e3(void)
 	/* Realtime Module Stop Control Register 1 */
 	cpg_write(RMSTPCR1,	0xFFFFFFFFU);
 	/* Realtime Module Stop Control Register 2 */
-	cpg_write(RMSTPCR2,	0x300E0FDCU);
+	cpg_write(RMSTPCR2,	0x000E0FDCU);
 	/* Realtime Module Stop Control Register 3 */
 	cpg_write(RMSTPCR3,	0xFFFFFFDFU);
 	/* Realtime Module Stop Control Register 4 */
@@ -328,7 +342,7 @@ static void bl2_system_cpg_init_e3(void)
 	/* System Module Stop Control Register 1 */
 	cpg_write(SMSTPCR1,	0xFFFFFFFFU);
 	/* System Module Stop Control Register 2 */
-	cpg_write(SMSTPCR2,	0x300E2FDCU);
+	cpg_write(SMSTPCR2,	0x000E2FDCU);
 	/* System Module Stop Control Register 3 */
 	cpg_write(SMSTPCR3,	0xFFFFFBDFU);
 	/* System Module Stop Control Register 4 */

plat/renesas/rcar/bl2_rcar_setup.c

@@ -130,10 +130,10 @@
 
 #if (RCAR_LSI == RCAR_E3)
 #define GPIO_INDT		(GPIO_INDT6)
-#define GPIO_BKUP_TRG		((uint32_t)1U<<13)
+#define GPIO_BKUP_TRG_SHIFT	((uint32_t)1U<<13U)
 #else  /* (RCAR_LSI == RCAR_E3) */
 #define GPIO_INDT		(GPIO_INDT1)
-#define GPIO_BKUP_TRG		((uint32_t)1U<<8)
+#define GPIO_BKUP_TRG_SHIFT	((uint32_t)1U<<8U)
 #endif /* (RCAR_LSI == RCAR_E3) */
 
 static uint32_t isDdrBackupMode(void);
@@ -702,7 +702,7 @@ void bl2_early_platform_setup(meminfo_t *mem_layout)
 
 /*******************************************************************************
  * Get DDR Backup Mode from GPIO
- *  BKUP_TRG(IO port A8, GPIO GP-0-8): LOW=Cold boot, HIGH=Warm boot
+ *  BKUP_TRG: LOW=Cold boot, HIGH=Warm boot
  * return: uint8_t
  *  0: DDR is not backup mode.
  *  1: DDR is backup mode.
@@ -714,8 +714,9 @@ static uint32_t isDdrBackupMode(void)
 	static uint32_t backupTrigger = 0U;
 	if (backupTriggerOnce == 1U) {
 		backupTriggerOnce = 0U;
-		/* Read and return BKUP_TRG(IO port B8, GPIO GP-1-8) */
-		if ((mmio_read_32((uintptr_t)GPIO_INDT) & GPIO_BKUP_TRG) != 0U) {
+		/* Read and return BKUP_TRG */
+		if ((mmio_read_32((uintptr_t)GPIO_INDT) &
+					GPIO_BKUP_TRG_SHIFT) != 0U) {
 			backupTrigger = 1U;
 		}
 	}
@@ -861,7 +862,7 @@ void bl2_plat_arch_setup(void)
 #if RCAR_BL2_DCACHE == 1
 	NOTICE("BL2: D-Cache enable\n");
 	rcar_configure_mmu_el1(BL2_BASE,
-			      (DEVICE_RCAR_BASE2 - BL2_BASE),
+			      (RCAR_SYSRAM_LIMIT - BL2_BASE),
 			      BL2_RO_BASE,
 			      BL2_RO_LIMIT
 #if USE_COHERENT_MEM

plat/renesas/rcar/ddr/ddr_a/boot_init_dram_regdef_e3.h

@@ -33,6 +33,8 @@
  * Revision history
  *
  * rev.0.01    2018/01/12    New
+ * rev.0.02    2018/02/27    add define DBSC_E3_DBCAM0CTRL0
+ * rev.0.03    2018/03/09    delete define DBSC_E3_DBCAM0CTRL0
  */
 
 #ifndef BOOT_INIT_DRAM_REGDEF_E3_H_
@@ -135,6 +137,9 @@ extern "C" {
 #define				CPG_CPGWPCR                0xE6150904U
 #define				CPG_SRSTCLR4               0xE6150950U
 
+/* MODE Monitor registers */
+
+#define				RST_MODEMR                 0xE6160060U
 
 #ifdef __cplusplus
 }