redefine rws bit field type

lib/rggen/systemverilog/ral.rb

@@ -27,7 +27,7 @@
     'ral/bit_field/type/rotrg_rwtrg_wotrg',
     'ral/bit_field/type/row0trg_row1trg_w0trg_w1trg',
     'ral/bit_field/type/rowo_rowotrg',
-    'ral/bit_field/type/rwc_rwhw',
+    'ral/bit_field/type/rwc_rwhw_rws',
     'ral/bit_field/type/rwe_rwl'
   ]
 end

lib/rggen/systemverilog/ral/bit_field/type/rwc_rwhw_rws.rb

@@ -0,0 +1,5 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, [:rwc, :rwhw, :rws]) do
+  sv_ral { access 'RW' }
+end

lib/rggen/systemverilog/rtl.rb

@@ -46,6 +46,7 @@
     'rtl/bit_field/type/rwc',
     'rtl/bit_field/type/rwe_rwl',
     'rtl/bit_field/type/rwhw',
+    'rtl/bit_field/type/rws',
     'rtl/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc',
     'rtl/bit_field/type/w0t_w1t',
     'rtl/bit_field/type/w0trg_w1trg',

lib/rggen/systemverilog/rtl/bit_field/type/rws.erb

@@ -0,0 +1,20 @@
+rggen_bit_field #(
+  .WIDTH          (<%= width %>),
+  .INITIAL_VALUE  (<%= initial_value %>),
+  .HW_SET_WIDTH   (1)
+) u_bit_field (
+  .i_clk              (<%= clock %>),
+  .i_rst_n            (<%= reset %>),
+  .bit_field_if       (<%= bit_field_if %>),
+  .o_write_trigger    (),
+  .o_read_trigger     (),
+  .i_sw_write_enable  ('1),
+  .i_hw_write_enable  ('0),
+  .i_hw_write_data    ('0),
+  .i_hw_set           (<%= set_signal %>),
+  .i_hw_clear         ('0),
+  .i_value            ('0),
+  .i_mask             ('1),
+  .o_value            (<%= value_out[loop_variables] %>),
+  .o_value_unmasked   ()
+);

lib/rggen/systemverilog/rtl/bit_field/type/rws.rb

@@ -0,0 +1,26 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, :rws) do
+  sv_rtl do
+    build do
+      unless bit_field.reference?
+        input :set, {
+          name: "i_#{full_name}_set", width: 1,
+          array_size: array_size, array_format: array_port_format
+        }
+      end
+      output :value_out, {
+        name: "o_#{full_name}", width: width,
+        array_size: array_size, array_format: array_port_format
+      }
+    end
+
+    main_code :bit_field, from_template: true
+
+    private
+
+    def set_signal
+      reference_bit_field || set[loop_variables]
+    end
+  end
+end

spec/rggen/systemverilog/ral/bit_field/type/rws_spec.rb

@@ -0,0 +1,29 @@
+
+# frozen_string_literal: true
+
+RSpec.describe 'bit_field/type/rws' do
+  include_context 'clean-up builder'
+  include_context 'bit field ral common'
+
+  before(:all) do
+    RgGen.enable(:bit_field, :type, [:rw, :rws])
+  end
+
+  specify 'アクセス属性はRW' do
+    sv_ral = create_sv_ral do
+      register do
+        name 'register_0'
+        bit_field { name 'bit_field_0'; bit_assignment lsb: 0; type :rws; initial_value 0 }
+        bit_field { name 'bit_field_1'; bit_assignment lsb: 1; type :rws; initial_value 0; reference 'register_1.bit_field_0' }
+      end
+
+      register do
+        name 'register_1'
+        bit_field { name 'bit_field_0'; bit_assignment lsb: 0; type :rw; initial_value 0 }
+      end
+    end
+
+    expect(sv_ral.bit_fields[0].access).to eq 'RW'
+    expect(sv_ral.bit_fields[1].access).to eq 'RW'
+  end
+end