Added GraphicsPicker

GraphicsPicker.vhd

@@ -0,0 +1,60 @@
+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date:    09:08:06 04/18/2012 
+-- Design Name: 
+-- Module Name:    GraphicsPicker - Behavioral 
+-- Project Name: 
+-- Target Devices: 
+-- Tool versions: 
+-- Description: 
+--
+-- Dependencies: 
+--
+-- Revision: 
+-- Revision 0.01 - File Created
+-- Additional Comments: 
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std;
+
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity GraphicsPicker is
+	Port ( 
+		clk : in  STD_LOGIC;
+		tile : in  STD_LOGIC_VECTOR (7 downto 0);
+		sprite : in  STD_LOGIC_VECTOR (7 downto 0);
+		x : in  integer range 0 to 530;
+		y : in  integer range 0 to 800;
+		graphics : out STD_LOGIC_VECTOR (7 downto 0)
+	);
+end GraphicsPicker;
+
+architecture Behavioral of GraphicsPicker is
+
+begin 
+process(clk)
+begin
+if rising_edge(clk) then
+	if y>200 then
+		graphics<=tile;	
+	else
+		graphics <= sprite;
+	end if;
+end if;
+end process;
+
+end Behavioral;
+

TestGrahpicsPicker.vhd

@@ -0,0 +1,103 @@
+--------------------------------------------------------------------------------
+-- Company: 
+-- Engineer:
+--
+-- Create Date:   09:26:22 04/18/2012
+-- Design Name:   
+-- Module Name:   C:/Documents and Settings/ricwi433/InputManager/TestGrahpicsPicker.vhd
+-- Project Name:  InputManager
+-- Target Device:  
+-- Tool versions:  
+-- Description:   
+-- 
+-- VHDL Test Bench Created by ISE for module: GraphicsPicker
+-- 
+-- Dependencies:
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes: 
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation 
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+USE ieee.numeric_std.ALL;
+ USE ieee.numeric_std.ALL;
+
+ENTITY TestGrahpicsPicker IS
+END TestGrahpicsPicker;
+
+ARCHITECTURE behavior OF TestGrahpicsPicker IS 
+
+    -- Component Declaration for the Unit Under Test (UUT)
+
+    COMPONENT GraphicsPicker
+    PORT(
+         clk : IN  std_logic;
+         tile : IN  std_logic_vector(7 downto 0);
+         sprite : IN  std_logic_vector(7 downto 0);
+         x : in integer range 0 to 530;
+         y : in integer range 0 to 800;
+         graphics : OUT  std_logic_vector(7 downto 0)
+        );
+    END COMPONENT;
+
+
+   --Inputs
+   signal clk : std_logic := '0';
+   signal tile : std_logic_vector(7 downto 0) := (others => '1');
+   signal sprite : std_logic_vector(7 downto 0) := (others => '0');
+   signal x : 	integer range 0 to 530 := 0 ;
+   signal y :  integer range 0 to 800 := 0 ;
+
+ 	--Outputs
+   signal graphics : std_logic_vector(7 downto 0);
+
+   -- Clock period definitions
+   constant clk_period : time := 10 ns;
+
+BEGIN
+
+	-- Instantiate the Unit Under Test (UUT)
+   uut: GraphicsPicker PORT MAP (
+          clk => clk,
+          tile => tile,
+          sprite => sprite,
+          x => x,
+          y => y,
+          graphics => graphics
+        );
+
+   -- Clock process definitions
+   clk_process :process
+   begin
+		clk <= '0';
+		wait for clk_period/2;
+		clk <= '1';
+		wait for clk_period/2;
+   end process;
+
+
+   -- Stimulus process
+   stim_proc: process
+   begin		
+      -- hold reset state for 100 ns.
+      wait for 100 ns;	
+		y<=300;
+      wait for clk_period*10;
+
+      -- insert stimulus here 
+
+      wait;
+   end process;
+
+END;